DAG: Lower fcNormal is.fpclass to compare with inf

[arsenm]

Looks worse for x86 without the fabs check. Not sure if
this is useful for any targets.

[arsenm]

• DAG: Lower fcNormal is.fpclass to compare with inf #100389 👈
• DAG: Lower single infinity is.fpclass tests to fcmp #100380
• DAG: Handle lowering unordered compare with inf #100378
• DAG: Check if is_fpclass is custom, instead of isLegalOrCustom #105577
• PPC: Custom lower ppcf128 is_fpclass if is_fpclass is custom #105540
• main

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[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-x86

Author: Matt Arsenault (arsenm)

Changes

Looks worse for x86 without the fabs check. Not sure if
this is useful for any targets.

---

Full diff: https://github.com/llvm/llvm-project/pull/100389.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+25)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 0036c182ab9db..4227f7bec9ec8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8652,6 +8652,31 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
       return DAG.getSetCC(DL, ResultVT, Op, Inf,
                           IsOrdered ? OrderedCmpOpcode : UnorderedCmpOpcode);
     }
+
+    if (FPTestMask == fcNormal) {
+      // TODO: Handle unordered
+      ISD::CondCode IsFiniteOp = IsInvertedFP ? ISD::SETUGE : ISD::SETOLT;
+      ISD::CondCode IsNormalOp = IsInvertedFP ? ISD::SETOLT : ISD::SETUGE;
+
+      if (isCondCodeLegalOrCustom(IsFiniteOp,
+                                  OperandVT.getScalarType().getSimpleVT()) &&
+          isCondCodeLegalOrCustom(IsNormalOp,
+                                  OperandVT.getScalarType().getSimpleVT()) &&
+          isFAbsFree(OperandVT)) {
+        // isnormal(x) --> fabs(x) < infinity && !(fabs(x) < smallest_normal)
+        SDValue Inf =
+            DAG.getConstantFP(APFloat::getInf(Semantics), DL, OperandVT);
+        SDValue SmallestNormal = DAG.getConstantFP(
+            APFloat::getSmallestNormalized(Semantics), DL, OperandVT);
+
+        SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op);
+        SDValue IsFinite = DAG.getSetCC(DL, ResultVT, Abs, Inf, IsFiniteOp);
+        SDValue IsNormal =
+            DAG.getSetCC(DL, ResultVT, Abs, SmallestNormal, IsNormalOp);
+        unsigned LogicOp = IsInvertedFP ? ISD::OR : ISD::AND;
+        return DAG.getNode(LogicOp, DL, ResultVT, IsFinite, IsNormal);
+      }
+    }
   }
 
   // Some checks may be represented as inversion of simpler check, for example

[jayfoad]

Looks worse for x86 without the fabs check. Not sure if this is useful for any targets.

Seems unlikely that this would ever be profitable in the ordered case, since you can implement that with pretty simple integer checks on the exponent field. (Check that it isn't 0 and isn't maximal.)

[arsenm]

ping

[RKSimon]

test coverage?

[arsenm]

test coverage?

This won't trigger on any target I know of

[RKSimon]

test coverage?

This won't trigger on any target I know of

So why bother?

[arsenm]

So why bother?

Completeness of inverting the instcombine transform, and I thought it would help but depends

[arsenm]

ping

[RKSimon]

No objections