Suboptimal register allocation which prevents the use of compressed instructions

[petrhosek]

https://godbolt.org/z/TjYxcYaTe shows the output from Clang and GCC for the following example:

int in1;
int in2;
int in3;
int in4;
int in5;
int in6;
int in7;
int in8;
int in9;
int in10;

int out1;
int out2;
int out3;
int out4;
int out5;
int out6;
int out7;
int out8;
int out9;
int out10;


void testit() {
    int x1 = in1+1;
    int x2 = in2+1;
    int x3 = in3+1;
    int x4 = in4+1;
    int x5 = in5+1;
    int x6 = in6+1;
    int x7 = in7+1;
    int x8 = in8+1;
    int x9 = in9+1;
    int x10 = in10+1;


    out1 = x1;
    out2 = x2;
    out3 = x3;
    out4 = x4;
    out5 = x5;
    out6 = x6;
    out7 = x7;
    out8 = x8;
    out9 = x9;
    out10 = x10;
}

When targeting Arm, LLVM reorders the operations only needing two registers, but when targeting RISC-V, it doesn't do that and ends up using too many registers which prevents the use of compressed instructions pessimizing the binary size. GCC appears to have the same issue.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Petr Hosek (petrhosek)

https://godbolt.org/z/TjYxcYaTe shows the output from Clang and GCC for the following example: ```c int in1; int in2; int in3; int in4; int in5; int in6; int in7; int in8; int in9; int in10;

int out1;
int out2;
int out3;
int out4;
int out5;
int out6;
int out7;
int out8;
int out9;
int out10;

void testit() {
int x1 = in1+1;
int x2 = in2+1;
int x3 = in3+1;
int x4 = in4+1;
int x5 = in5+1;
int x6 = in6+1;
int x7 = in7+1;
int x8 = in8+1;
int x9 = in9+1;
int x10 = in10+1;

out1 = x1;
out2 = x2;
out3 = x3;
out4 = x4;
out5 = x5;
out6 = x6;
out7 = x7;
out8 = x8;
out9 = x9;
out10 = x10;

}

When targeting Arm, LLVM reorders the operations only needing two registers, but when targeting RISC-V, it doesn't do that and ends up using too many registers which prevents the use of compressed instructions pessimizing the binary size. GCC appears to have the same issue.
</details>

[topperc]

-misched=ilpmin or -misched=ilpmax seems to improve it.

[wangpc-pp]

-misched=ilpmin or -misched=ilpmax seems to improve it.

Do we need to change schedule strategy when optimizing for size?

[topperc]

We generate more compressible addi instructions if I disable the C extension.

[topperc]

This also makes it generate more compressible addis

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 30457f528853..64385483625f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -746,7 +746,7 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
 
 unsigned
 RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
-  return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 1 : 0;
+  return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 0 : 0;
 }
 
 // Add two address hints to improve chances of being able to use a compressed

[topperc]

Adding -mllvm -riscv-enable-global-merge doesn't fix the addi register allocation problem, but does remove a lot of LUI instructions.