[AMDGPU][MC] Many MIMG opcodes do not accept tfe with dmask:0xf

[dpreobra]

Bugzilla Link	39300
Version	trunk
OS	All
CC	@atamazov,@jayfoad,@arsenm

Extended Description

The reason for this issue is that current implementation does not support 5-register tuples.

[jayfoad]

I think this is fixed now. See https://reviews.llvm.org/D94960 which enabled proper disassembly of MIMG instructions with tfe.

[dpreobra]

Thanks! The patch you mentioned did fix a lot of disassembler failures.

However some tests with 0xf dmask still fail to disassemble.

For example, the following code is disassembled ok for gfx8 and gfx9:

0x00,0x0f,0x44,0xf0,0xfc,0x05,0x02,0x00
image_atomic_cmpswap v[5:8], v252, s[8:15] dmask:0xf

The same code with tfe produces an invalid output for the same GPUs:

0x00,0x0f,0x45,0xf0,0xfc,0x05,0x02,0x00
image_atomic_cmpswap v[5:6], v252, s[8:15] dmask:0xf tfe

Also the following instruction fails to assemble on gfx7-gfx10:

image_atomic_cmpswap v[5:9], v252, s[8:15] dmask:0xf tfe

See also related bugs 48846, 48847

[jwanggit86]

I think this problem is now fixed with PR 112622.

[arsenm]

Seems to work now