Description
| Bugzilla Link | 35784 |
| Version | trunk |
| OS | Windows NT |
| Depends On | #39267 |
| Blocks | #31672 |
| CC | @adibiagio,@topperc,@rotateright,@ZviRackover |
Extended Description
Split off from Bug #26183.
With the scheduler models maturing we should be investigating ways to better select between MC optimizations based on scheduler characteristics, register pressure etc.
Bug #26183 mentioned several X86 slow/fast features that could be replaced with scheduler costings:
FeatureSlowBTMem
FeatureSlowSHLD
FeatureSlowUAMem16
FeatureSlowUAMem32
FeatureSlowDivide32
FeatureSlowDivide64
Some of these affect (older) CPUs that currently don't have a accurate scheduler models - taking numbers from Agner is probably enough to be useful?
Additionally, the use of when to combine multiple shuffles to a single variable shuffle mask keeps coming up. As well as the actual instruction cost, the cost of loading the mask needs to be accurately modelled: register pressure? can it be hoisted? etc.