[HLSL][SPIRV] Hitting assert when compiling program with splitdouble version of asuint

[spall]

Hitting an assert when compiling this program with -spirv

StructuredBuffer<double4> In0 : register(t0);
RWStructuredBuffer<uint4> Lows : register(u1);
RWStructuredBuffer<uint4> Highs : register(u2);

[numthreads(1,1,1)]
void main() {

  asuint(In0[0], Lows[0], Highs[0]);
  uint4 Tmp0;
  uint4 Tmp1;
  asuint(In0[1].xyz, Tmp0.xyz, Tmp1.xyz);
  asuint(In0[1].w, Tmp0.w, Tmp1.w);
  Lows[1] = Tmp0;
  Highs[1]= Tmp1;
  asuint(In0[2].xy, Tmp0.xy, Tmp1.xy);
  asuint(In0[2].zw, Tmp0.zw, Tmp1.zw);
  Lows[2] = Tmp0;
  Highs[2] = Tmp1;
  asuint(double4(10, 0, 5.57, 111.111), Lows[3], Highs[3]);
}

Assertion failed: TargetType->getNumElements() <= SourceType->getNumElements(), file llvm-project/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp, line 77

https://godbolt.org/z/jPPGb48vo

[farzonl]

The assert ia correctly firing, but the logic is likely too basic. We are trying to convert a vec4 of double to a vec8 of int to match the type of the shuffle vector However the assert doesn't seem to be correct because a double is a f64 and an int is 32 bits. So the assert should consider word sizes not just vector element sizes. @Keenuts Does that sound right?

%8 = shufflevector <8 x i32> %4, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

(lldb) expr Source->dump()
  %9 = tail call noundef align 32 dereferenceable(32) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4f64_12_0t(target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) %6, i32 0)
(lldb) expr TargetType->dump()
<8 x i32>
(lldb) expr SourceType->dump()
<4 x double>

Full llvm IR dump

@.str = private unnamed_addr constant [4 x i8] c"In0\00", align 1
@.str.2 = private unnamed_addr constant [5 x i8] c"Lows\00", align 1
@.str.4 = private unnamed_addr constant [6 x i8] c"Highs\00", align 1

; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none)
define void @main() local_unnamed_addr #0 {
entry:
  %0 = tail call target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0v4f64_12_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str)
  %1 = tail call target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0v4i32_12_1t(i32 0, i32 1, i32 1, i32 0, i1 false, ptr nonnull @.str.2)
  %2 = tail call target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0v4i32_12_1t(i32 0, i32 2, i32 1, i32 0, i1 false, ptr nonnull @.str.4)
  %3 = tail call noundef align 32 dereferenceable(32) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4f64_12_0t(target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) %0, i32 0)
  %4 = load <8 x i32>, ptr addrspace(11) %3, align 32
  %5 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %1, i32 0)
  %6 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %2, i32 0)
  %7 = shufflevector <8 x i32> %4, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %8 = shufflevector <8 x i32> %4, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i32> %7, ptr addrspace(11) %5, align 16
  store <4 x i32> %8, ptr addrspace(11) %6, align 16
  %9 = tail call noundef align 32 dereferenceable(32) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4f64_12_0t(target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) %0, i32 1)
  %10 = load <4 x double>, ptr addrspace(11) %9, align 32
  %11 = shufflevector <4 x double> %10, <4 x double> poison, <3 x i32> <i32 0, i32 1, i32 2>
  %12 = bitcast <3 x double> %11 to <6 x i32>
  %13 = shufflevector <6 x i32> %12, <6 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 poison>
  %14 = shufflevector <6 x i32> %12, <6 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 poison>
  %15 = extractelement <4 x double> %10, i64 3
  %16 = bitcast double %15 to <2 x i32>
  %17 = shufflevector <2 x i32> %16, <2 x i32> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison>
  %18 = shufflevector <2 x i32> %16, <2 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
  %19 = shufflevector <4 x i32> %13, <4 x i32> %18, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
  %20 = shufflevector <4 x i32> %14, <4 x i32> %17, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  %21 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %1, i32 1)
  store <4 x i32> %19, ptr addrspace(11) %21, align 16
  %22 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %2, i32 1)
  store <4 x i32> %20, ptr addrspace(11) %22, align 16
  %23 = tail call noundef align 32 dereferenceable(32) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4f64_12_0t(target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) %0, i32 2)
  %24 = load <4 x double>, ptr addrspace(11) %23, align 32
  %25 = shufflevector <4 x double> %24, <4 x double> poison, <2 x i32> <i32 0, i32 1>
  %26 = bitcast <2 x double> %25 to <4 x i32>
  %27 = shufflevector <4 x double> %24, <4 x double> poison, <2 x i32> <i32 2, i32 3>
  %28 = bitcast <2 x double> %27 to <4 x i32>
  %29 = shufflevector <4 x i32> %26, <4 x i32> %28, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %30 = shufflevector <4 x i32> %26, <4 x i32> %28, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %31 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %1, i32 2)
  store <4 x i32> %29, ptr addrspace(11) %31, align 16
  %32 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %2, i32 2)
  store <4 x i32> %30, ptr addrspace(11) %32, align 16
  %33 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %1, i32 3)
  %34 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %2, i32 3)
  store <4 x i32> <i32 0, i32 0, i32 536870912, i32 -1610612736>, ptr addrspace(11) %33, align 16
  store <4 x i32> <i32 1076101120, i32 0, i32 1075201966, i32 1079756570>, ptr addrspace(11) %34, align 16
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0v4f64_12_0t(i32, i32, i32, i32, i1, ptr) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0v4i32_12_1t(i32, i32, i32, i32, i1, ptr) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4f64_12_0t(target("spirv.VulkanBuffer", [0 x <4 x double>], 12, 0), i32) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1), i32) #1

attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "approx-func-fp-math"="true" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }

[farzonl]

So I supressed the assert by doing

diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
index 75055072573b..cd32a0d97a6a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
@@ -74,7 +74,10 @@ class SPIRVLegalizePointerCast : public FunctionPass {
   // Returns the loaded value.
   Value *loadVectorFromVector(IRBuilder<> &B, FixedVectorType *SourceType,
                               FixedVectorType *TargetType, Value *Source) {
-    assert(TargetType->getNumElements() <= SourceType->getNumElements());
+    const DataLayout &DL = B.GetInsertBlock()->getModule()->getDataLayout();               
+    TypeSize TargetTypeSize = DL.getTypeSizeInBits(TargetType);
+    TypeSize SourceTypeSize = DL.getTypeSizeInBits(SourceType);
+    assert(TargetTypeSize <= SourceTypeSize);
     LoadInst *NewLoad = B.CreateLoad(SourceType, Source);
     buildAssignType(B, SourceType, NewLoad);
     Value *AssignValue = NewLoad;

However that is causing problems ins the SPIRV ASM Printer

LLVM ERROR: Unable to meet SPIR-V requirements for this target.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ../llvm_debug_build/bin/llc -O0 -verify-machineinstrs -mtriple=spirv-unknown-vulkan test.ll -o -
1.      Running pass 'Function Pass Manager' on module 'test.ll'.
2.      Running pass 'SPIRV Assembly Printer' on function '@main'
 #0 0x00005a0886d5ec2d llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/Unix/Signals.inc:834:11
 #1 0x00005a0886d5f1ab PrintStackTraceSignalHandler(void*) /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/Unix/Signals.inc:918:1
 #2 0x00005a0886d5cf46 llvm::sys::RunSignalHandlers() /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/Signals.cpp:104:5
 #3 0x00005a0886d5f94d SignalHandler(int, siginfo_t*, void*) /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/Unix/Signals.inc:426:38
 #4 0x000077724f242520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
 #5 0x000077724f2969fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
 #6 0x000077724f2969fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10
 #7 0x000077724f2969fc pthread_kill ./nptl/pthread_kill.c:89:10
 #8 0x000077724f242476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
 #9 0x000077724f2287f3 abort ./stdlib/abort.c:81:7
#10 0x00005a0886c7557d llvm::report_fatal_error(llvm::Twine const&, bool) /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/ErrorHandling.cpp:137:5
#11 0x00005a0886c753f2 /mnt/DevDrive/projects/llvm-project/llvm/lib/Support/ErrorHandling.cpp:96:3
#12 0x00005a0883e18ad5 llvm::SPIRV::RequirementHandler::checkSatisfiable(llvm::SPIRVSubtarget const&) const /mnt/DevDrive/projects/llvm-project/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp:775:1
#13 0x00005a0883e08e5d (anonymous namespace)::SPIRVAsmPrinter::outputGlobalRequirements() /mnt/DevDrive/projects/llvm-project/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp:379:13
#14 0x00005a0883e08c80 (anonymous namespace)::SPIRVAsmPrinter::outputModuleSections() /mnt/DevDrive/projects/llvm-project/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp:618:3
#15 0x00005a0883e08a51 (anonymous namespace)::SPIRVAsmPrinter::emitFunctionHeader() /mnt/DevDrive/projects/llvm-project/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp:150:5
#16 0x00005a08850f33c3 llvm::AsmPrinter::emitFunctionBody() /mnt/DevDrive/projects/llvm-project/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1889:3
#17 0x00005a088336590e llvm::AsmPrinter::runOnMachineFunction(llvm::MachineFunction&) /mnt/DevDrive/projects/llvm-project/llvm/include/llvm/CodeGen/AsmPrinter.h:455:5
#18 0x00005a08855bd81b llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /mnt/DevDrive/projects/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:108:8
#19 0x00005a0885db974a llvm::FPPassManager::runOnFunction(llvm::Function&) /mnt/DevDrive/projects/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1398:23
#20 0x00005a0885dbe102 llvm::FPPassManager::runOnModule(llvm::Module&) /mnt/DevDrive/projects/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1444:16
#21 0x00005a0885db9ffb (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /mnt/DevDrive/projects/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1513:23
#22 0x00005a0885db9b7a llvm::legacy::PassManagerImpl::run(llvm::Module&) /mnt/DevDrive/projects/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:531:16
#23 0x00005a0885dbe3e1 llvm::legacy::PassManager::run(llvm::Module&) /mnt/DevDrive/projects/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1640:3
#24 0x00005a088207450b compileModule(char**, llvm::LLVMContext&) /mnt/DevDrive/projects/llvm-project/llvm/tools/llc/llc.cpp:761:9
#25 0x00005a08820725f1 main /mnt/DevDrive/projects/llvm-project/llvm/tools/llc/llc.cpp:404:13
#26 0x000077724f229d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#27 0x000077724f229e40 call_init ./csu/../csu/libc-start.c:128:20
#28 0x000077724f229e40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#29 0x00005a0882071da5 _start (../llvm_debug_build/bin/llc+0x6769da5)
Aborted (core dumped)

The issue seems to be with vectors of size 8. We seem to be blowing up on the below instructions:

%11 = call <8 x i32> @llvm.spv.bitcast.v8i32.v4f64(<4 x double> %10)
 call void @llvm.spv.assign.type.v8i32(<8 x i32> %11, metadata <8 x i32> poison)
 %12 = shufflevector <8 x i32> %11, <8 x i32> %11, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>

Oddly enough even though it is v8 thats causing things to break the Capability thats saying this isnt satisfyable is:

(lldb) expr Cap
(llvm::SPIRV::Capability::Capability) $4 = Vector16

llvm-project/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines 753 to 760 in 69e4514

	for (auto Cap : MinimalCaps) {
	if (AvailableCaps.contains(Cap) && !AvoidCaps.S.contains(Cap))
	continue;
	LLVM_DEBUG(dbgs() << "Capability not supported: "
	<< getSymbolicOperandMnemonic(
	OperandCategory::CapabilityOperand, Cap)
	<< "\n");
	IsSatisfiable = false;

[s-perron]

You might need to do more than just change the assert in that way. The spv_bitcast is only legal if the target type and source type have the same bit width. I would divide it into two separate cases.

1. Bitwidth of target type and source type are the same, so just do a bitcast and return.
2. Otherwise assert that the elements types are the same and the number of elements in the target is less than the number of elements in the source. In this case, do the vector shuffle.

We can add a new case where they have different bit sizes and different element types later.

The other problem is that vectors in vulkan can not have more than 4 elements. That will have to be fixed up somewhere. I don't know the best place to do that. The vector16 capability is not available for shaders.

[Keenuts]

We are trying to convert a vec4 of double to a vec8 of int to

I'm not sure I understand the HLSL:
https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-asuint

is asuint returning a vec8 in this case?

float4 f4;
asuint(f4, f4);

[farzonl]

We are trying to convert a vec4 of double to a vec8 of int to

I'm not sure I understand the HLSL: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-asuint

is asuint returning a vec8 in this case?

float4 f4;
asuint(f4, f4);

You are looking at the wrong asuint docs. This is the right one: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/asuint

What is happening with asuint(In0[0], Lows[0], Highs[0]); Is that the double (first argument) is being split into two uints one for the low and high bytes.

What seems to be breaking is the lowering of shufflevector from llvm ir to spirv

llvm-project/clang/lib/CodeGen/CGHLSLBuiltins.cpp

Lines 151 to 152 in 7b467bc

	LowBits = CGF->Builder.CreateShuffleVector(Uint32Vec, EvenMask);
	HighBits = CGF->Builder.CreateShuffleVector(Uint32Vec, OddMask);

.

It might be that we need to change handleHlslSplitdouble to not do shufflevector but that would have implications on the DirectX backend so didn't want to make that change just yet.

To follow along the full implementation grep for __builtin_hlsl_elementwise_splitdouble

llvm-project/clang/lib/Headers/hlsl/hlsl_intrinsics.h

Lines 94 to 110 in 7b467bc

	//===----------------------------------------------------------------------===//
	// asuint splitdouble builtins
	//===----------------------------------------------------------------------===//
	/// \fn void asuint(double D, out uint lowbits, out int highbits)
	/// \brief Split and interprets the lowbits and highbits of double D into uints.
	/// \param D The input double.
	/// \param lowbits The output lowbits of D.
	/// \param highbits The output highbits of D.
	_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_splitdouble)
	void asuint(double, out uint, out uint);
	_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_splitdouble)
	void asuint(double2, out uint2, out uint2);
	_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_splitdouble)
	void asuint(double3, out uint3, out uint3);
	_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_splitdouble)
	void asuint(double4, out uint4, out uint4);

llvm-project/clang/lib/CodeGen/CGHLSLBuiltins.cpp

Lines 778 to 784 in 7b467bc

	case Builtin::BI__builtin_hlsl_elementwise_splitdouble: {
	assert((E->getArg(0)->getType()->hasFloatingRepresentation() &&
	E->getArg(1)->getType()->hasUnsignedIntegerRepresentation() &&
	E->getArg(2)->getType()->hasUnsignedIntegerRepresentation()) &&
	"asuint operands types mismatch");
	return handleHlslSplitdouble(E, this);

[Keenuts]

Ah thanks, I see.
Because for each element you want to extract the low and high, the 64-bit x N is converted into 32-bit * 2N which indeed generates a cool IR to achieve this.
Using arrays wouldn't allow to workaround the v4 limit for SPIR-V (since we wouldn't be able to bitcast the double4 into a uint[8]).

To what extend changing the IR to use 4-elements vectors would impact you?
(Since HLSL forbids vectors of more than 4 elements, I was hoping to keep this assumption in the backend)

If there is a large impact, I suppose we'd need to add a legalization pass in the backend to get rid of any vector larger than 4