InstCombine misses freeze of i1 select fold which appears in X86ISelLowering

[arsenm]

define i1 @src(i8 range(i8 0, 2) noundef %i, i8 range(i8 0, 2) noundef %i1) {
bb:
  %loadedv.i.i2.i = trunc nuw i8 %i to i1
  %loadedv.i1.i.i = trunc nuw i8 %i1 to i1
  %i2 = select i1 %loadedv.i.i2.i, i1 %loadedv.i1.i.i, i1 false
  %cond.fr13 = freeze i1 %i2
  ret i1 %cond.fr13
}

define i1 @tgt(i8 range(i8 0, 2) noundef %i, i8 range(i8 0, 2) noundef %i1) {
bb:
  %i21 = and i8 %i1, %i
  %i2 = trunc nuw i8 %i21 to i1
  ret i1 %i2
}

https://alive2.llvm.org/ce/z/HRpvwJ

I noticed this while looking at random IR samples in X86ISelLowering.cpp's output.

[nikic]

We should probably be more aggressive about pushing freeze upwards in cases where it can be done by dropping flags only (rather than inserting multiple freezes).

[BaoshanPang]

It seems eventually the redudant instructions are eliminated:

https://alive2.llvm.org/ce/z/-erq2F

[arsenm]

It seems eventually the redudant instructions are eliminated:

https://alive2.llvm.org/ce/z/-erq2F

I may have over-reduced the example. This is closer to the original pattern:

define i1 @src(ptr readonly captures(none) %arg, ptr readonly captures(none) %HasCX16.i.i.i) {
bb:
  %i = load i8, ptr %HasCX16.i.i.i, align 8, !range !0, !noundef !1
  %loadedv.i.i2.i = trunc nuw i8 %i to i1
  %Is64Bit.i.i.i = getelementptr inbounds nuw i8, ptr %arg, i64 445
  %i1 = load i8, ptr %Is64Bit.i.i.i, align 1, !range !0
  %loadedv.i1.i.i = trunc nuw i8 %i1 to i1
  %i2 = select i1 %loadedv.i.i2.i, i1 %loadedv.i1.i.i, i1 false
  %cond.fr13 = freeze i1 %i2
  ret i1 %cond.fr13
}

define i1 @tgt(ptr readonly captures(none) %arg, ptr readonly captures(none) %HasCX16.i.i.i) #0 {
bb:
  %i = load i8, ptr %HasCX16.i.i.i, align 8, !range !0, !noundef !1
  %Is64Bit.i.i.i = getelementptr inbounds nuw i8, ptr %arg, i64 445
  %i1 = load i8, ptr %Is64Bit.i.i.i, align 1, !range !0
  %i1.fr = freeze i8 %i1
  %i21 = and i8 %i1.fr, %i
  %i2 = trunc nuw i8 %i21 to i1
  ret i1 %i2
}

!0 = !{i8 0, i8 2}
!1 = !{}

opt -O3 | llc has more instructions

[BaoshanPang]

still same:

https://alive2.llvm.org/ce/z/bWRKVD

[arsenm]

still same:

https://alive2.llvm.org/ce/z/bWRKVD

On x86. aarch64 has more instructions: https://alive2.llvm.org/ce/z/aCobwf