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[RISCV] Can't select f16 extract_vector_elt with zfhmin #110126

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lukel97 opened this issue Sep 26, 2024 · 2 comments · Fixed by #110144
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[RISCV] Can't select f16 extract_vector_elt with zfhmin #110126

lukel97 opened this issue Sep 26, 2024 · 2 comments · Fixed by #110144

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@lukel97
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lukel97 commented Sep 26, 2024

define half @f(<vscale x 4 x half> %v) {
  %x = extractelement <vscale x 4 x half> %v, i32 0
  ret half %x
}

With -mattr=+v,+zfhmin,+zvfhmin (or +zfh) we fail to select the extract_vector_elt:

LLVM ERROR: Cannot select: t5: f16 = extract_vector_elt t2, Constant:i64<0>
  t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
    t1: nxv4f16 = Register %0
  t3: i64 = Constant<0>

However with only -mattr=+v,+zvfhmin we can lower this because the f16 gets softened:

Optimized lowered selection DAG: %bb.0 'f:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
              t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
            t5: f16 = extract_vector_elt t2, Constant:i64<0>
          t6: i16 = bitcast t5
        t7: i32 = any_extend t6
      t9: i32 = or t7, Constant:i32<-65536>
    t10: f32 = bitcast t9
  t12: ch,glue = CopyToReg t0, Register:f32 $f10_f, t10
  t13: ch = RISCVISD::RET_GLUE t12, Register:f32 $f10_f, t12:1



Type-legalized selection DAG: %bb.0 'f:'
SelectionDAG has 12 nodes:
  t0: ch,glue = EntryToken
            t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
          t15: nxv4i16 = bitcast t2
        t21: i64 = extract_vector_elt t15, Constant:i64<0>
      t18: i64 = or t21, Constant:i64<-65536>
    t20: f32 = RISCVISD::FMV_W_X_RV64 t18
  t12: ch,glue = CopyToReg t0, Register:f32 $f10_f, t20
  t13: ch = RISCVISD::RET_GLUE t12, Register:f32 $f10_f, t12:1
@llvmbot
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llvmbot commented Sep 26, 2024

@llvm/issue-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

```llvm define half @f(<vscale x 4 x half> %v) { %x = extractelement <vscale x 4 x half> %v, i32 0 ret half %x } ```

With -mattr=+v,+zfhmin,+zvfhmin (or +zfh) we fail to select the extract_vector_elt:

LLVM ERROR: Cannot select: t5: f16 = extract_vector_elt t2, Constant:i64&lt;0&gt;
  t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
    t1: nxv4f16 = Register %0
  t3: i64 = Constant&lt;0&gt;

However with only -mattr=+v,+zvfhmin we can lower this because the f16 gets softened:

Optimized lowered selection DAG: %bb.0 'f:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
              t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
            t5: f16 = extract_vector_elt t2, Constant:i64&lt;0&gt;
          t6: i16 = bitcast t5
        t7: i32 = any_extend t6
      t9: i32 = or t7, Constant:i32&lt;-65536&gt;
    t10: f32 = bitcast t9
  t12: ch,glue = CopyToReg t0, Register:f32 $f10_f, t10
  t13: ch = RISCVISD::RET_GLUE t12, Register:f32 $f10_f, t12:1



Type-legalized selection DAG: %bb.0 'f:'
SelectionDAG has 12 nodes:
  t0: ch,glue = EntryToken
            t2: nxv4f16,ch = CopyFromReg t0, Register:nxv4f16 %0
          t15: nxv4i16 = bitcast t2
        t21: i64 = extract_vector_elt t15, Constant:i64&lt;0&gt;
      t18: i64 = or t21, Constant:i64&lt;-65536&gt;
    t20: f32 = RISCVISD::FMV_W_X_RV64 t18
  t12: ch,glue = CopyToReg t0, Register:f32 $f10_f, t20
  t13: ch = RISCVISD::RET_GLUE t12, Register:f32 $f10_f, t12:1

lukel97 added a commit to lukel97/llvm-project that referenced this issue Sep 26, 2024
This is the f64/f32 version of llvm#109774.
I've left out f16 and bf16 for now because there's a separate issue where we can't select extract_vector_elt when f16/bf16 is a legal type, see llvm#110126.
@lukel97
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lukel97 commented Sep 26, 2024

I should also mention that we have the same issue for bf16 and zfbfmin with zvfbfmin

lukel97 added a commit to lukel97/llvm-project that referenced this issue Sep 26, 2024
When the scalar type is illegal, it gets softened during type legalization and gets lowered as an integer.

However with zfhmin/zfbfmin the type is now legal and it passes through type legalization where it crashes because we didn't have any custom lowering or patterns for it.

This handles said case via the existing custom lowering to a vslidedown and vfmv.f.s.
It also handles the case where we only have zvfhmin/zvfbfmin and don't have vfmv.f.s, in which case we need to extract it to a GPR and then use fmv.h.x.

Fixes llvm#110126
lukel97 added a commit that referenced this issue Sep 27, 2024
…110144)

When the scalar type is illegal, it gets softened during type
legalization and gets lowered as an integer.

However with zfhmin/zfbfmin the type is now legal and it passes through
type legalization where it crashes because we didn't have any custom
lowering or patterns for it.

This handles said case via the existing custom lowering to a vslidedown
and vfmv.f.s.
It also handles the case where we only have zvfhmin/zvfbfmin and don't
have vfmv.f.s, in which case we need to extract it to a GPR and then use
fmv.h.x.

Fixes #110126
lukel97 added a commit that referenced this issue Sep 27, 2024
This is the f64/f32 version of #109774.
I've left out f16 and bf16 for now because there's a separate issue
where we can't select extract_vector_elt when f16/bf16 is a legal type,
see #110126.
Sterling-Augustine pushed a commit to Sterling-Augustine/llvm-project that referenced this issue Sep 27, 2024
…lvm#110144)

When the scalar type is illegal, it gets softened during type
legalization and gets lowered as an integer.

However with zfhmin/zfbfmin the type is now legal and it passes through
type legalization where it crashes because we didn't have any custom
lowering or patterns for it.

This handles said case via the existing custom lowering to a vslidedown
and vfmv.f.s.
It also handles the case where we only have zvfhmin/zvfbfmin and don't
have vfmv.f.s, in which case we need to extract it to a GPR and then use
fmv.h.x.

Fixes llvm#110126
Sterling-Augustine pushed a commit to Sterling-Augustine/llvm-project that referenced this issue Sep 27, 2024
This is the f64/f32 version of llvm#109774.
I've left out f16 and bf16 for now because there's a separate issue
where we can't select extract_vector_elt when f16/bf16 is a legal type,
see llvm#110126.
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