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[RISCV] Handle f16/bf16 extract_vector_elt when scalar type is legal (llvm#110144)
When the scalar type is illegal, it gets softened during type legalization and gets lowered as an integer. However with zfhmin/zfbfmin the type is now legal and it passes through type legalization where it crashes because we didn't have any custom lowering or patterns for it. This handles said case via the existing custom lowering to a vslidedown and vfmv.f.s. It also handles the case where we only have zvfhmin/zvfbfmin and don't have vfmv.f.s, in which case we need to extract it to a GPR and then use fmv.h.x. Fixes llvm#110126
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1082,8 +1082,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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VT, Custom);
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MVT EltVT = VT.getVectorElementType();
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if (isTypeLegal(EltVT))
1085-
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT}, VT,
1086-
Custom);
1085+
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT,
1086+
ISD::EXTRACT_VECTOR_ELT},
1087+
VT, Custom);
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else
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setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT},
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EltVT, Custom);
@@ -8990,6 +8991,16 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, Idx);
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}
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8994+
if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
8995+
EltVT == MVT::bf16) {
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// If we don't have vfmv.f.s for f16/bf16, extract to a gpr then use fmv.h.x
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MVT IntVT = VecVT.changeTypeToInteger();
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SDValue IntVec = DAG.getBitcast(IntVT, Vec);
8999+
SDValue IntExtract =
9000+
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, IntVec, Idx);
9001+
return DAG.getNode(RISCVISD::FMV_H_X, DL, EltVT, IntExtract);
9002+
}
9003+
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// If this is a fixed vector, we need to convert it to a scalable vector.
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MVT ContainerVT = VecVT;
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if (VecVT.isFixedLengthVector()) {

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