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[Xtensa] Move XtensaUtils to MCTargetDesc
PR #121118 attempted to introduce `checkRegister` used by XtensaDisassembler. Since `checkRegister` and other functions in XtensaUtils.cpp cannot link against XtensaCodeGen, move them to XtensaDesc, which can be used by XtensaDisassembler. Pull Request: #123969
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7 files changed

+56
-91
lines changed

7 files changed

+56
-91
lines changed

llvm/lib/Target/Xtensa/CMakeLists.txt

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@@ -24,7 +24,6 @@ add_llvm_target(XtensaCodeGen
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XtensaRegisterInfo.cpp
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XtensaSubtarget.cpp
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XtensaTargetMachine.cpp
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XtensaUtils.cpp
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LINK_COMPONENTS
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AsmPrinter

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

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@@ -32,6 +32,48 @@
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using namespace llvm;
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bool Xtensa::isValidAddrOffset(int Scale, int64_t OffsetVal) {
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bool Valid = false;
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switch (Scale) {
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case 1:
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Valid = (OffsetVal >= 0 && OffsetVal <= 255);
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break;
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case 2:
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Valid = (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);
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break;
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case 4:
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Valid = (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);
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break;
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default:
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break;
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}
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return Valid;
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}
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bool Xtensa::isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset) {
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int Scale = 0;
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switch (Opcode) {
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case Xtensa::L8UI:
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case Xtensa::S8I:
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Scale = 1;
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break;
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case Xtensa::L16SI:
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case Xtensa::L16UI:
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case Xtensa::S16I:
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Scale = 2;
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break;
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case Xtensa::LEA_ADD:
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return (Offset >= -128 && Offset <= 127);
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default:
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// assume that MI is 32-bit load/store operation
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Scale = 4;
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break;
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}
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return isValidAddrOffset(Scale, Offset);
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}
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static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT,
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const MCTargetOptions &Options) {

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h

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@@ -28,6 +28,7 @@ class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class MachineInstr;
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class StringRef;
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class Target;
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class raw_ostream;
@@ -43,6 +44,15 @@ MCAsmBackend *createXtensaMCAsmBackend(const Target &T,
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const MCTargetOptions &Options);
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std::unique_ptr<MCObjectTargetWriter>
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createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian);
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namespace Xtensa {
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// Check address offset for load/store instructions.
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// The offset should be multiple of scale.
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bool isValidAddrOffset(int Scale, int64_t OffsetVal);
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// Check address offset for load/store instructions.
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bool isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset);
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} // namespace Xtensa
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} // end namespace llvm
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// Defines symbolic names for Xtensa registers.

llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp

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@@ -10,9 +10,9 @@
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
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#include "Xtensa.h"
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#include "XtensaTargetMachine.h"
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#include "XtensaUtils.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
@@ -75,7 +75,7 @@ class XtensaDAGToDAGISel : public SelectionDAGISel {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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int64_t OffsetVal = CN->getSExtValue();
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Valid = isValidAddrOffset(Scale, OffsetVal);
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Valid = Xtensa::isValidAddrOffset(Scale, OffsetVal);
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if (Valid) {
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// If the first operand is a FI, get the TargetFI Node.

llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

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@@ -11,9 +11,9 @@
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//===----------------------------------------------------------------------===//
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#include "XtensaRegisterInfo.h"
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
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#include "XtensaInstrInfo.h"
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#include "XtensaSubtarget.h"
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#include "XtensaUtils.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -99,7 +99,7 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int64_t Offset =
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SPOffset + (int64_t)StackSize + MI.getOperand(FIOperandNum + 1).getImm();
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bool Valid = isValidAddrOffset(MI, Offset);
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bool Valid = Xtensa::isValidAddrOffsetForOpcode(MI.getOpcode(), Offset);
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// If MI is not a debug value, make sure Offset fits in the 16-bit immediate
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// field.

llvm/lib/Target/Xtensa/XtensaUtils.cpp

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llvm/lib/Target/Xtensa/XtensaUtils.h

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