[CIR][CIRGen] Support OpenCL Vector Types #613

seven-mile · 2024-05-16T18:33:48Z

Resolve #532 .

Support CIRGen of ExtVectorElementExpr that includes swizzle v.xyx and subscription v.s0.

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

clang/test/CIR/Lowering/vectype-cl.cpp

clang/test/CIR/CodeGen/vectype-cl.cpp

bcardosolopes

Way to go on the skeleton work and thanks for fixing the testcase, more comments inline.

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

clang/lib/CIR/CodeGen/CIRGenValue.h

seven-mile · 2024-06-01T17:02:09Z

Test cases improved. Tell me if I missed something! ; )

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

jopperm

(The free-function nits are in reference to https://mlir.llvm.org/deprecation/; please check all occurrences in this PR.)

clang/lib/CIR/CodeGen/CIRGenBuilder.h

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

clang/test/CIR/CodeGen/vectype-ext.cpp

seven-mile · 2024-06-03T13:34:45Z

Nice catch! I appreciate it. Updated.

Removed test cases for int7 and the code path to support odd-component vectors. Will submit the patch for 3-component vectors and the removed part afterward.

bcardosolopes

LGTM after one minor pending inline question! Thanks!

[CIR][NFC] Arrange test cases [CIR][NFC] Use ArrayAttr for elts [CIR][NFC] Test store one element and make HLSL NYI [CIR][NFC] Add test for one element load line 687 of CIRGenExpr.cpp [CIR][NFC] Fix untagged values [CIR][NFC] Add test for extended-sized vec store for branch: line 755 in CIRGenExpr.cpp # Conflicts: # clang/test/CIR/CodeGen/vectype-ext.cpp [CIR][NFC] Add test for undefined position in odd-component vectors

…reatment

clang/test/CIR/CodeGen/vectype-ext.cpp

bcardosolopes · 2024-06-06T22:16:39Z

clang/test/CIR/CodeGen/vectype-ext.cpp

+  // CIR: %{{[0-9]+}} = cir.vec.create(%{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}} : !s32i, !s32i, !s32i, !s32i) : !cir.vector<!s32i x 4>
+  // LLVM:      %[[#X1:]] = load i32, ptr %{{[0-9]+}}, align 4
+  // LLVM-NEXT: %[[#X2:]] = load i32, ptr %{{[0-9]+}}, align 4
+  // LLVM-NEXT: %[[#SUM:]] = add i32 %[[#X2]], 1


If we look at how LLVM currently codegen for this, we get a add nsw instead of a plain add, see https://godbolt.org/z/xdevh38r8. There are probably other differences too.

I believe its not related to this specific PR, but to set expectations: whenever LLVM checks are written, that should not be done blindly, we should actually check it against what traditional (OG) codegen currently emits. If there are semantic differences, they ideally should be fixed as part of the PR, but if not, we should create an issue so someone else could take a look later.

I'll create an issue for this one, can you please go through the rest of the file and see if you can spot more differences and create issues for them? Thanks in advance!

Done in #664

Many thanks for finding out this diff! I actually went through the final LLVM IR and compared them, but missed this overflow flag quite carelessly.

After a double check, I found the default index types used by two paths are different: i64 for CIR and i32 for Clang. But if user is using other types(like vec[x: i32 or i64]), in both paths, they will be preserved as is. This PR chose i64 because the previous works from @dkolsen-pgi have already done it. Since they are all self-consistent, I don't think it's a problem.

Nothing else special.

Sounds good to me, thanks for double checking the rest!

…d store (#674) Continue the work of #613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (llvm#674) Continue the work of llvm#613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (llvm#674) Continue the work of llvm#613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (llvm#674) Continue the work of llvm#613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (llvm#674) Continue the work of llvm#613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve #532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (#674) Continue the work of #613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

Resolve #532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

…d store (#674) Continue the work of #613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

seven-mile marked this pull request as ready for review May 16, 2024 18:38

seven-mile mentioned this pull request May 17, 2024

Fix InitListExpr for OpenCL vectors #615

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bcardosolopes requested changes May 18, 2024

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seven-mile force-pushed the opencl-vec-types branch from 7fb1234 to ded43cc Compare May 20, 2024 01:28

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seven-mile force-pushed the opencl-vec-types branch from ded43cc to b47be43 Compare June 1, 2024 16:59

seven-mile commented Jun 1, 2024

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jopperm reviewed Jun 3, 2024

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bcardosolopes approved these changes Jun 3, 2024

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seven-mile added 9 commits June 4, 2024 16:19

[CIR][NFC] Use vi7 instead to workaround dependency on vec3 special t…

3fd0829

…reatment

[CIR][NFC] Categorize test cases

da0724a

feature mark

8d75348

[CIR][NFC] Add LLVM test for build_lvalue

214d3a4

[CIR][NFC] Pin cpp standard to 17 in tests

95dae0d

[CIR][NFC] Use free function form of cast isa and dyn_cast

b42e43e

[CIR][CodeGen] Remove invalid int7 test cases

bb05de1

[CIR] Fix after rebase

3531b74

seven-mile force-pushed the opencl-vec-types branch from 8f01283 to 3531b74 Compare June 4, 2024 08:29

bcardosolopes reviewed Jun 5, 2024

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clang/test/CIR/CodeGen/vectype-ext.cpp Show resolved Hide resolved

[CIR][NFC] Add LLVM test results

9e5ab94

bcardosolopes approved these changes Jun 6, 2024

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bcardosolopes mentioned this pull request Jun 6, 2024

Vector related arith missing nsw on addition #664

Closed

bcardosolopes merged commit a949a65 into llvm:main Jun 6, 2024

This was referenced Jun 7, 2024

Single-operand vector shuffling #667

Open

[CIR][CodeGen] Special treatment of 3-element extended vector load and store #674

Merged

seven-mile mentioned this pull request Jun 15, 2024

[GSoC] Add OpenCL support to compile GPU kernels #689

Closed

bruteforceboy pushed a commit to bruteforceboy/clangir that referenced this pull request Oct 2, 2024

[CIR][CIRGen] Support OpenCL Vector Types (llvm#613)

c04acc8

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

Hugobros3 pushed a commit to shady-gang/clangir that referenced this pull request Oct 2, 2024

[CIR][CIRGen] Support OpenCL Vector Types (llvm#613)

cc1c7d1

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

smeenai pushed a commit to smeenai/clangir that referenced this pull request Oct 9, 2024

[CIR][CIRGen] Support OpenCL Vector Types (llvm#613)

46e3cfb

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

keryell pushed a commit to keryell/clangir that referenced this pull request Oct 19, 2024

[CIR][CIRGen] Support OpenCL Vector Types (llvm#613)

3e24a42

Resolve llvm#532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

lanza pushed a commit that referenced this pull request Nov 5, 2024

[CIR][CIRGen] Support OpenCL Vector Types (#613)

d7dc87f

Resolve #532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

lanza pushed a commit that referenced this pull request Nov 5, 2024

[CIR][CodeGen] Special treatment of 3-element extended vector load an…

b217246

…d store (#674) Continue the work of #613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

lanza pushed a commit that referenced this pull request Mar 18, 2025

[CIR][CIRGen] Support OpenCL Vector Types (#613)

56e2b4f

Resolve #532 . Support CIRGen of `ExtVectorElementExpr` that includes swizzle `v.xyx` and subscription `v.s0`.

lanza pushed a commit that referenced this pull request Mar 18, 2025

[CIR][CodeGen] Special treatment of 3-element extended vector load an…

1455b29

…d store (#674) Continue the work of #613 . Original CodeGen treat vec3 as vec4 to get aligned memory access. This PR enable these paths.

[CIR][CIRGen] Support OpenCL Vector Types #613

[CIR][CIRGen] Support OpenCL Vector Types #613

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seven-mile commented May 16, 2024 •

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