Skip to content

[SYCL][ESIMD][EMU] Enable dpas with ESIMD_EMULATOR backend #6475

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 15 commits into from
Aug 16, 2022
Merged

[SYCL][ESIMD][EMU] Enable dpas with ESIMD_EMULATOR backend #6475

Changes from all commits
Commits
Show all changes
15 commits
Select commit Hold shift + click to select a range
0bb5952
[SYCL][ESIMD][EMU] Enabling dpas with ESIMD_EMULATOR backend
dongkyunahn-intel Jul 25, 2022
b28d750
Working version for dpas.cpp
dongkyunahn-intel Jul 26, 2022
64d375b
Separating definitions of __esimd_dpas* per __SYCL_DEVICE_ONLY__
dongkyunahn-intel Jul 26, 2022
fc3bd07
Unifying __esimd_dpas* functions
dongkyunahn-intel Jul 28, 2022
a621dd8
Missing changes in unifying __esimd_dpas* functions
dongkyunahn-intel Jul 28, 2022
b698423
systolic_depth decoding bug fix
dongkyunahn-intel Jul 28, 2022
a47893c
Fix for passing dpas_test.cpp
dongkyunahn-intel Jul 28, 2022
0e220e9
Fixing 'odr' test failure
dongkyunahn-intel Jul 29, 2022
1960d87
Reverting clang-formatting for '__esimd_dpas_inner'
dongkyunahn-intel Jul 29, 2022
3907816
Reverting (void*) work-around
dongkyunahn-intel Jul 29, 2022
27ab022
Bugfix for dpas_test.cpp test failure
dongkyunahn-intel Jul 30, 2022
1707460
Changing dpas_info funtion argument into template argument for host mode
dongkyunahn-intel Aug 8, 2022
d06821a
Removing unnecessary changes
dongkyunahn-intel Aug 12, 2022
063b905
Applying suggestions
dongkyunahn-intel Aug 12, 2022
1615f45
Working version
dongkyunahn-intel Aug 15, 2022
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
27 changes: 11 additions & 16 deletions sycl/include/sycl/ext/intel/experimental/esimd/detail/math_intrin.hpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,10 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T, N)
}
#endif // __SYCL_DEVICE_ONLY__

#ifdef __SYCL_DEVICE_ONLY__

// TODO: __esimd_dpas* should have single declaration for host and device:
// Ret __esimd_dpas*(...)
template <typename T, typename T0, typename T1, typename T2, int N, int N1,
int N2>
SYCL_EXTERNAL SYCL_ESIMD_FUNCTION __ESIMD_DNS::vector_type_t<T, N>
Expand All @@ -135,7 +139,7 @@ SYCL_EXTERNAL SYCL_ESIMD_FUNCTION __ESIMD_DNS::vector_type_t<T, N>
__esimd_dpasw2(__ESIMD_DNS::vector_type_t<T1, N1> src1,
__ESIMD_DNS::vector_type_t<T2, N2> src2, int dpas_info);

#ifndef __SYCL_DEVICE_ONLY__
#else // __SYCL_DEVICE_ONLY__

template <typename T0, typename T1, int SZ>
__ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
Expand Down Expand Up @@ -459,10 +463,10 @@ __esimd_dpas_bits_precision(__ESIMD_ENS::argument_type precisionType) {

template <__ESIMD_ENS::argument_type src1_precision,
__ESIMD_ENS::argument_type src2_precision, int systolic_depth,
int repeat_count, typename RT, typename T1, typename T2,
int repeat_count, typename RT, typename T0, typename T1, typename T2,
__ESIMD_NS::uint SZ, __ESIMD_NS::uint N1, __ESIMD_NS::uint N2>
inline __ESIMD_DNS::vector_type_t<RT, SZ>
__esimd_dpas_inner(const __ESIMD_DNS::vector_type_t<RT, SZ> *src0,
__esimd_dpas_inner(const __ESIMD_DNS::vector_type_t<T0, SZ> *src0,
const __ESIMD_DNS::vector_type_t<T1, N1> &src1,
const __ESIMD_DNS::vector_type_t<T2, N2> &src2) {
__ESIMD_DNS::vector_type_t<RT, SZ> retv;
Expand Down Expand Up @@ -647,7 +651,8 @@ __esimd_dpas_inner(const __ESIMD_DNS::vector_type_t<RT, SZ> *src0,
static_cast<short>(reinterpret_cast<uint32_t &>(tmpUint) >> 16);
} else
retv[r * SIMDSize + n] =
__ESIMD_EMU_DNS::satur<RT>::saturate(simdAcc[n], sat1);
__ESIMD_EMU_DNS::satur<RT>::template saturate<TmpAccEl>(simdAcc[n],
sat1);
}

} // Repeat.
Expand All @@ -663,14 +668,9 @@ inline __ESIMD_DNS::vector_type_t<T, N>
__esimd_dpas(__ESIMD_DNS::vector_type_t<T0, N> src0,
__ESIMD_DNS::vector_type_t<T1, N1> src1,
__ESIMD_DNS::vector_type_t<T2, N2> src2) {
#ifdef __SYCL_EXPLICIT_SIMD_PLUGIN__
return __esimd_dpas_inner<src1_precision, src2_precision, systolic_depth,
repeat_count, T, T1, T2, N, N1, N2>(
repeat_count, T, T0, T1, T2, N, N1, N2>(
std::addressof(src0), src1, src2);
#else // __SYCL_EXPLICIT_SIMD_PLUGIN__
__ESIMD_UNSUPPORTED_ON_HOST;
return __ESIMD_DNS::vector_type_t<T, N>();
#endif // __SYCL_EXPLICIT_SIMD_PLUGIN__
}

template <__ESIMD_ENS::argument_type src1_precision,
Expand All @@ -680,14 +680,9 @@ template <__ESIMD_ENS::argument_type src1_precision,
inline __ESIMD_DNS::vector_type_t<T, N>
__esimd_dpas2(__ESIMD_DNS::vector_type_t<T1, N1> src1,
__ESIMD_DNS::vector_type_t<T2, N2> src2) {
#ifdef __SYCL_EXPLICIT_SIMD_PLUGIN__
return __esimd_dpas_inner<src1_precision, src2_precision, systolic_depth,
repeat_count, T, T1, T2, N, N1, N2>(nullptr, src1,
repeat_count, T, T, T1, T2, N, N1, N2>(nullptr, src1,
src2);
#else // __SYCL_EXPLICIT_SIMD_PLUGIN__
__ESIMD_UNSUPPORTED_ON_HOST;
return __ESIMD_DNS::vector_type_t<T, N>();
#endif // __SYCL_EXPLICIT_SIMD_PLUGIN__
}

template <__ESIMD_ENS::argument_type src1_precision,
Expand Down