Issue #2 tuning #3
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ali1234
suggested changes
Mar 28, 2021
| cx_write(MO_AGC_GAIN_ADJ3, (0x28<<16)|(0x28<<8)|(0x50<<0)); | ||
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| /* Disable PLL adjust (stabilizes output when video is detected by chip) */ | ||
| cx_write(MO_PLL_ADJ_CTRL, cx_read(MO_PLL_ADJ_CTRL) & ~(0x0<<25)); |
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This line doesn't alter the value of MO_PLL_ADJ_CTRL. It should be ~(0x1<<25) to set PLL_ADJ_EN to 0.
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