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[arm64] the prolog generation for arm64 doesn't support holes in regMasks. #11606

@sandreenko

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@sandreenko

There were many offline discussions about that issue that was found by our desktop testing so I want to open it here to summarize what we decided to do with that.

genPushCalleeSavedRegisters determinates registers that need to be saved in the prolog and expect no holes between them. However, we can't always guarantee that contract; holes can appear at least in stress mode testing.

genSaveCalleeSavedRegistersHelp uses no-holes contract to use save_pair and restore_pair optimization, so when it is not true it hits an assert.

The repro was added by dotnet/coreclr#21344.

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arch-arm64area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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