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SystemVerilog: propagation for <->, ===, !== works #853

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Nov 26, 2024
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SystemVerilog: propagation for <->, ===, !== works #853

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6 changes: 3 additions & 3 deletions regression/verilog/expressions/constants2.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,13 @@ module main;
parameter p28 = 1&&1;
parameter p29 = 1||1;
parameter p30 = 1->1;
// parameter p31 = 1<->1;
parameter p31 = 1<->1;
parameter p32 = 1<1;
parameter p33 = 1<=1;
parameter p34 = 1>1;
parameter p35 = 1>=1;
// parameter p36 = 1===1;
// parameter p37 = 1!==1;
parameter p36 = 1===1;
parameter p37 = 1!==1;
parameter p38 = 1==1;
parameter p39 = 1!=1;
parameter p40 = 1==?1;
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