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Verilog: test modules/parameters7 passes #695

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Merged
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Sep 17, 2024
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Verilog: test modules/parameters7 passes #695

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3 changes: 1 addition & 2 deletions regression/verilog/modules/parameters7.desc
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Original file line number Diff line number Diff line change
@@ -1,8 +1,7 @@
KNOWNBUG
CORE
parameters7.sv

^EXIT=0$
^SIGNAL=0$
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The test fails owing to the missing grammar for typing parameters.