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This repairs the output of the Verilog (not: SVA) implication operator, to read ->, and not |->.

This repairs the output of the Verilog (not: SVA) implication operator, to
read ->, and not |->.
@kroening kroening marked this pull request as ready for review September 10, 2024 15:05
@tautschnig tautschnig merged commit 96f8d09 into main Sep 11, 2024
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@tautschnig tautschnig deleted the fixup-verilog-implies branch September 11, 2024 10:00
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
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