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SystemVerilog: restrict statement #676

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Merged
merged 1 commit into from
Sep 10, 2024
Merged

SystemVerilog: restrict statement #676

merged 1 commit into from
Sep 10, 2024

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kroening
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@kroening kroening commented Sep 8, 2024

This adds the SystemVerilog restrict statement.

@kroening kroening marked this pull request as ready for review September 8, 2024 23:01
tautschnig
tautschnig approved these changes Sep 9, 2024
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Could do with a test.

@kroening
SystemVerilog: restrict statement
04d4dbc 
This adds the SystemVerilog restrict statement.
@kroening kroening merged commit 3847085 into main Sep 10, 2024
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@kroening kroening deleted the restrict1 branch September 10, 2024 01:51
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
@kroening
Merge pull request diffblue#676 from diffblue/restrict1
5079a26 
SystemVerilog: `restrict` statement
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@tautschnig tautschnig tautschnig approved these changes

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@kroening @tautschnig