aval/bval lowering for Verilog logical equality #656
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kroening
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tautschnig
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src/verilog/aval_bval_encoding.cpp
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| exprt make_x() | ||
| { | ||
| auto type = verilog_unsignedbv_typet{1}; | ||
| return lower_to_aval_bval(constant_exprt{"x", type}); |
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Shouldn't we have ID_x for this?
== and != return 'x' when either operand contains x or z. This lowers the operator to the aval/bval encoding.
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==and!=returnxwhen either operand containsxorz. This lowers the operator to the aval/bval encoding.