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aval/bval lowering for Verilog logical equality #656

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Merged
merged 1 commit into from
Sep 4, 2024

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== and != return x when either operand contains x or z. This lowers the operator to the aval/bval encoding.

@kroening kroening force-pushed the verilog_equality_lowering branch 3 times, most recently from 4d7e284 to fcffffa Compare September 1, 2024 12:57
@kroening kroening marked this pull request as ready for review September 1, 2024 13:00
exprt make_x()
{
auto type = verilog_unsignedbv_typet{1};
return lower_to_aval_bval(constant_exprt{"x", type});
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Shouldn't we have ID_x for this?

== and != return 'x' when either operand contains x or z.  This lowers the
operator to the aval/bval encoding.
@kroening kroening force-pushed the verilog_equality_lowering branch from fcffffa to 15b9299 Compare September 4, 2024 14:18
@kroening kroening merged commit f25aad5 into main Sep 4, 2024
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@kroening kroening deleted the verilog_equality_lowering branch September 4, 2024 14:35
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