SystemVerilog: assertion statements use hierarchical identifiers #576
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Assertion statements with a block label have regular hierarchical identifiers, and do not use a separate "property" name space. The behavior for SMV-style assertion statements is unchanged. Assertion statements without block item now get a label based on the kind of the assertion item (assert/assume/cover).
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tautschnig
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Jun 24, 2024
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Assertion statements with a block label have regular hierarchical identifiers, and do not use a separate "property" name space. The behavior for SMV-style assertion statements is unchanged.
Assertion statements without block item now get a label based on the kind of the assertion item (assert/assume/cover).