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Verilog: add a KNOWNBUG test for a for loop over a register #241

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Merged
merged 1 commit into from
Dec 4, 2023

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@kroening kroening commented Dec 4, 2023

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@kroening kroening marked this pull request as ready for review December 4, 2023 21:47
@@ -0,0 +1,7 @@
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Should this be KNOWNBUG?

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Well, it shouldn't be!

@tautschnig tautschnig merged commit fe49803 into main Dec 4, 2023
@tautschnig tautschnig deleted the for_with_reg branch December 4, 2023 23:46
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2 participants