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Make the counter synthesizable, update comment #1414

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Make the counter synthesizable, update comment #1414

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dbd1e7f
Make the counter synthesizable, update comment
ShashankVM Nov 15, 2025
a0b312b
Fix syntax for module declaration in counter2.sv
ShashankVM Nov 15, 2025
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21 changes: 11 additions & 10 deletions regression/ebmc/ranking-function/counter2.sv
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Original file line number Diff line number Diff line change
@@ -1,16 +1,17 @@
// count down from 10 to 0
// count up from 0 to 10

module main(input clk);
module main(
input logic clk,
input logic reset,
output logic [3:0] counter);

reg [3:0] counter;

initial counter = 0;

always @(posedge clk)
if(counter != 10)
counter = counter + 1;
always_ff @(posedge clk or posedge reset)
if (reset)
counter <= 'b0;
else if (counter != 10)
counter <= counter + 1;

// expected to pass
p0: assert property (s_eventually counter == 10);
ASSERT_COUNTER_EVENTUALLY_10: assert property (@(posedge clk) disable iff (reset) s_eventually (counter == 10));

endmodule