SystemVerilog: ++/-- for generate for
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kroening
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tautschnig
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Aug 19, 2025
src/verilog/verilog_generate.cpp
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| throw errort().with_location(for_statement.source_location()) | ||
| << "unexpected genvar_iteration item"; |
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Shouldn't this be some sort of PRECONDITION or DATA_INVARIANT instead? I don't think a user should be able to trigger this.
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Replaced by DATA_INVARIANT
SystemVerilog generate for allows both pre- and post-increment and -decrement.
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SystemVerilog generate
forallows both pre- and post-increment and -decrement.