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9 changes: 9 additions & 0 deletions regression/verilog/synthesis/part_select2.desc
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
part_select2.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The non constant index for the part select assignment is not supported.
14 changes: 14 additions & 0 deletions regression/verilog/synthesis/part_select2.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
module main(input clk, input [3:0] index);

reg [31:0] t;

always_ff @(posedge clk) begin
// The LHS of the part select does not have to be constant.
t[index*2 +: 2] = 'b01;

// should pass
assert(t[index*2] == 1);
assert(t[index*2+1] == 0);
end

endmodule
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