Skip to content

SystemVerilog: assignment patterns with structure keys #1000

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Feb 20, 2025

Conversation

kroening
Copy link
Member

No description provided.

This adds 1800-2017 assignment patters with keys for struct types.
@kroening kroening force-pushed the structure_pattern_key branch from ec33684 to 24d6e6d Compare February 19, 2025 15:40
@kroening kroening marked this pull request as ready for review February 19, 2025 15:42
@tautschnig tautschnig merged commit b07f60d into main Feb 20, 2025
9 checks passed
@tautschnig tautschnig deleted the structure_pattern_key branch February 20, 2025 11:36
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants