SystemVerilog: assignment patterns with structure keys

Author: kroening

src/verilog/parser.y

@@ -3649,8 +3649,26 @@ open_value_range: value_range;
 // A.6.7.1 Patterns
 
 assignment_pattern:
-	'\'' '{' expression_brace '}'
+	  '\'' '{' expression_brace '}'
 		{ init($$, ID_verilog_assignment_pattern); swapop($$, $3); }
+	| '\'' '{' structure_pattern_key_brace '}'
+		{ init($$, ID_verilog_assignment_pattern); swapop($$, $3); }
+	;
+
+structure_pattern_key_and_expression:
+	  structure_pattern_key ':' expression
+		{ init($$, ID_member_initializer); mto($$, $1); mto($$, $3); }
+	;
+
+structure_pattern_key_brace:
+	  structure_pattern_key_and_expression
+		{ init($$); mto($$, $1); }
+	| structure_pattern_key_brace structure_pattern_key_and_expression
+		{ $$ = $1; mto($$, $2); }
+	;
+
+structure_pattern_key:
+	  member_identifier
 	;
 
 assignment_pattern_expression:
@@ -4456,6 +4474,8 @@ ps_covergroup_identifier:
 
 memory_identifier: identifier;
 
+member_identifier: identifier;
+
 method_identifier: identifier;
 
 signal_identifier: identifier;