Skip to content

Commit 812cd30

Browse files
committed
SystemVerilog: assignment patterns with structure keys
1 parent c7a04c0 commit 812cd30

File tree

1 file changed

+21
-1
lines changed

1 file changed

+21
-1
lines changed

src/verilog/parser.y

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3649,8 +3649,26 @@ open_value_range: value_range;
36493649
// A.6.7.1 Patterns
36503650

36513651
assignment_pattern:
3652-
'\'' '{' expression_brace '}'
3652+
'\'' '{' expression_brace '}'
36533653
{ init($$, ID_verilog_assignment_pattern); swapop($$, $3); }
3654+
| '\'' '{' structure_pattern_key_brace '}'
3655+
{ init($$, ID_verilog_assignment_pattern); swapop($$, $3); }
3656+
;
3657+
3658+
structure_pattern_key_and_expression:
3659+
structure_pattern_key ':' expression
3660+
{ init($$, ID_member_initializer); mto($$, $1); mto($$, $3); }
3661+
;
3662+
3663+
structure_pattern_key_brace:
3664+
structure_pattern_key_and_expression
3665+
{ init($$); mto($$, $1); }
3666+
| structure_pattern_key_brace structure_pattern_key_and_expression
3667+
{ $$ = $1; mto($$, $2); }
3668+
;
3669+
3670+
structure_pattern_key:
3671+
member_identifier
36543672
;
36553673

36563674
assignment_pattern_expression:
@@ -4456,6 +4474,8 @@ ps_covergroup_identifier:
44564474

44574475
memory_identifier: identifier;
44584476

4477+
member_identifier: identifier;
4478+
44594479
method_identifier: identifier;
44604480

44614481
signal_identifier: identifier;

0 commit comments

Comments
 (0)