.clif Test Case
test compile
set opt_level=speed
target x86_64
function u0:9(i8) -> i16 system_v {
block0(v0: i8):
    v8 = sextend.i16 v0
    v9 = imul v8, v8
    v10 = iconst.i64 1000
    v13 = sshr v9, v10  ; v10 = 1000
    return v13
}
 
Steps to Reproduce
- Compile the above test case.
 
Expected Results
Compiles fine and masks the shift amount as expected.
Actual Results
Panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)"
Versions and Environment
Cranelift version or commit: Tested with 0.104 and b6a8abc.
Operating system: N/A
Architecture: x86_64
Extra Info
Reported to cg_clif by @cbeuw in rust-lang/rustc_codegen_cranelift#1455.