@@ -519,7 +519,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
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setOperationAction (ISD::TRAP, MVT::Other, Legal);
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setTargetDAGCombine ({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
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- ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL});
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+ ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
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+ ISD::SIGN_EXTEND});
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if (Subtarget.isGP64bit ())
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setMaxAtomicSizeInBitsSupported (64 );
@@ -1213,6 +1214,27 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
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DAG.getConstant (SMSize, DL, MVT::i32 ));
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}
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+ static SDValue performSignExtendCombine (SDNode *N, SelectionDAG &DAG,
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+ TargetLowering::DAGCombinerInfo &DCI,
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+ const MipsSubtarget &Subtarget) {
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+ SDValue N0 = N->getOperand (0 );
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+ EVT VT = N->getValueType (0 );
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+
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+ // Pattern match XOR.
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+ // $dst = sign_extend (xor (trunc $src), imm)
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+ // => xor $src, imm'
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+ if (N0.getOpcode () == ISD::XOR &&
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+ N0.getOperand (0 ).getOpcode () == ISD::TRUNCATE &&
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+ N0.getOperand (1 ).getOpcode () == ISD::Constant) {
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+ SDValue X0 = N0.getOperand (0 ).getOperand (0 );
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+ APInt Mask = N0.getConstantOperandAPInt (1 ).zext (VT.getSizeInBits ());
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+ return DAG.getNode (ISD::XOR, SDLoc (N0), VT, X0,
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+ DAG.getTargetConstant (Mask, SDLoc (N0), VT));
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+ }
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+
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+ return SDValue ();
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+ }
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+
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SDValue MipsTargetLowering::PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI)
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const {
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SelectionDAG &DAG = DCI.DAG ;
@@ -1238,6 +1260,8 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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return performSHLCombine (N, DAG, DCI, Subtarget);
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case ISD::SUB:
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return performSUBCombine (N, DAG, DCI, Subtarget);
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+ case ISD::SIGN_EXTEND:
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+ return performSignExtendCombine (N, DAG, DCI, Subtarget);
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}
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return SDValue ();
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