Skip to content

Commit 6f5113d

Browse files
committed
[MIPS]Optimize ((sign_extend (xor (trunc X), imm)) to (xor (X, imm")
Fix llvm#99783
1 parent 86d65ae commit 6f5113d

File tree

4 files changed

+314
-168
lines changed

4 files changed

+314
-168
lines changed

llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
519519
setOperationAction(ISD::TRAP, MVT::Other, Legal);
520520

521521
setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
522-
ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL});
522+
ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
523+
ISD::SIGN_EXTEND});
523524

524525
if (Subtarget.isGP64bit())
525526
setMaxAtomicSizeInBitsSupported(64);
@@ -1213,6 +1214,27 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
12131214
DAG.getConstant(SMSize, DL, MVT::i32));
12141215
}
12151216

1217+
static SDValue performSignExtendCombine(SDNode *N, SelectionDAG &DAG,
1218+
TargetLowering::DAGCombinerInfo &DCI,
1219+
const MipsSubtarget &Subtarget) {
1220+
SDValue N0 = N->getOperand(0);
1221+
EVT VT = N->getValueType(0);
1222+
1223+
// Pattern match XOR.
1224+
// $dst = sign_extend (xor (trunc $src), imm)
1225+
// => xor $src, imm'
1226+
if (N0.getOpcode() == ISD::XOR &&
1227+
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1228+
N0.getOperand(1).getOpcode() == ISD::Constant) {
1229+
SDValue X0 = N0.getOperand(0).getOperand(0);
1230+
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
1231+
return DAG.getNode(ISD::XOR, SDLoc(N0), VT, X0,
1232+
DAG.getTargetConstant(Mask, SDLoc(N0), VT));
1233+
}
1234+
1235+
return SDValue();
1236+
}
1237+
12161238
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
12171239
const {
12181240
SelectionDAG &DAG = DCI.DAG;
@@ -1238,6 +1260,8 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
12381260
return performSHLCombine(N, DAG, DCI, Subtarget);
12391261
case ISD::SUB:
12401262
return performSUBCombine(N, DAG, DCI, Subtarget);
1263+
case ISD::SIGN_EXTEND:
1264+
return performSignExtendCombine(N, DAG, DCI, Subtarget);
12411265
}
12421266

12431267
return SDValue();

0 commit comments

Comments
 (0)