Use the ADI's DMA as VDMA #172
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Since device_prep_interleaved_dma() is already implemented, the DMA_INTERLEAVE capability should be set. Signed-off-by: Dragos Bogdan <[email protected]>
The HDL graphics core can be interfaced with any VDMA (e.g., Analog Devices AXI-DMAC DMA controller), not only with the Xilinx one. Signed-off-by: Dragos Bogdan <[email protected]>
The Video DMA must support cyclic transfers. To make sure that the transfer will be an interleaved cyclic one, pass the CYCLIC flag to the DMA driver, so it can enable this option. Signed-off-by: Dragos Bogdan <[email protected]>
dbogdan
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commodo,
lclausen-adi,
mhennerich,
mirceacaprioru and
stefpopa
drivers/dma/dma-axi-dmac.c
Outdated
| desc->sg[0].y_len = 1; | ||
| } | ||
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| if (chan->hw_cyclic && (flags & DMA_CYCLIC)) |
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Drop the chan->hw_cyclic. If the DMA does not support hardware cyclic mode it should fallback to software cyclic rather than ignoring the flag.
| adi,source-bus-type = <0>; | ||
| adi,destination-bus-width = <64>; | ||
| adi,destination-bus-type = <1>; | ||
| adi,length-width = <24>; |
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the length-width property has been made optional and is no longer required.
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I knew this. :) Sorry.
An example when this mode can be enabled is where the controller is used as a Video DMA. Signed-off-by: Dragos Bogdan <[email protected]>
An example when these two bits should be enabled simultaneously is where the controller is used as a Video DMA and the TLAST signal acts as an "end of frame" signal. Signed-off-by: Dragos Bogdan <[email protected]>
This change is required according to the HDL reference design's updates. Signed-off-by: Dragos Bogdan <[email protected]>
| vdma_config.park = 1; | ||
| vdma_config.coalesc = 0xff; | ||
| xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config); | ||
| if (!strncmp(axi_hdmi_crtc->dma->device->dev->driver->name, "xilinx-vdma", 11)) { |
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nitpick: the reference expansion here is a bit long; but I don't know of a better solution atm;
| xlnx,datawidth = <0x40>; | ||
| xlnx,genlock-mode = <0x0>; | ||
| xlnx,include-dre = <0x0>; | ||
| interrupts = <0 59 0>; |
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curios: the interrupt types have changed; is this is intended ?
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It should be 4. The ADI DMA interrupt is level-high triggered. But I think the IRQ controller pretty much ignores this anyway so we haven't really been paying attention to this in the past.
If you want a project for a slow afternoon go through all the existing devicetrees and fix the interrupt levels.
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Ack.
Maybe we'll mark this in an issue tracker and see when we do this.
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Otherwise looks good |
commodo
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commodo
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LGTM
Will merge this later today if no objections
This should be merged when the corresponding HDL changes will be also merged:
analogdevicesinc/hdl#106