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projects/adrv9026: Improve design #1956

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projects/adrv9026: Upgrade design
AndrDragomir Nov 13, 2025
434381c
docs/adrv9026: Update documentation
AndrDragomir Nov 17, 2025
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48 changes: 27 additions & 21 deletions docs/projects/adrv9026/adrv9026_nls_block_diagram.svg
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108 changes: 58 additions & 50 deletions docs/projects/adrv9026/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -200,10 +200,11 @@ Example block design for Single link and RX OBS in Non-LinkSharing mode

The Rx links (ADC Path) operate with the following parameters:

- Rx Framer parameters: L=2, M=4, F=4, S=1, NP=16, N=16
- Sample Rate: 245.76 MSPS
- Rx Framer parameters: L=2, M=8, F=8, S=1, NP=16, N=16
- Sample Rate: 122.88 MSPS
- Dual link: No
- RX_DEVICE_CLK: 245.76 MHz (Lane Rate/40)
- RX_DEVICE_CLK: 122.88 MHz
- RX_LINK_CLK: 245.76 MHz (Lane Rate/40)
- REF_CLK: 245.76 MHz (Lane Rate/40)
- JESD204B Lane Rate: 9.83 Gbps
- CPLL
Expand Down Expand Up @@ -374,6 +375,7 @@ The following are the parameters of this project that can be configured:
- [RX/TX/RX_OS]_JESD_L: number of lanes per link
- [RX/TX/RX_OS]_JESD_S: number of samples per frame
- [RX/TX/RX_OS]_JESD_NP: number of bits per sample
- [RX/TX/RX_OS]_TPL_WIDTH : TPL data path width in bits
- [RX/TX/RX_OS]_NUM_LINKS: number of links

Clock scheme
Expand Down Expand Up @@ -674,49 +676,55 @@ configure this project, depending on the carrier used.

.. collapsible:: Default values of the make parameters for ADRV9026

+-------------------+------------------------------------------------------+
| Parameter | Default value of the parameters depending on carrier |
+-------------------+---------------------------+--------------------------+
| | ZCU102/VCU118 | A10SoC |
+===================+===========================+==========================+
| JESD_MODE | 8B10B | 8B10B |
+-------------------+---------------------------+--------------------------+
| ORX_ENABLE | 0 | --- |
+-------------------+---------------------------+--------------------------+
| RX_LANE_RATE | 9.83 | 9.83 |
+-------------------+---------------------------+--------------------------+
| TX_LANE_RATE | 9.83 | 9.83 |
+-------------------+---------------------------+--------------------------+
| TX_NUM_LINKS | 1 | 1 |
+-------------------+---------------------------+--------------------------+
| RX_NUM_LINKS | 1 | 1 |
+-------------------+---------------------------+--------------------------+
| RX_OS_NUM_LINKS | 1 | --- |
+-------------------+---------------------------+--------------------------+
| RX_JESD_M | 8 | 8 |
+-------------------+---------------------------+--------------------------+
| RX_JESD_L | 4 | 4 |
+-------------------+---------------------------+--------------------------+
| RX_JESD_S | 1 | 1 |
+-------------------+---------------------------+--------------------------+
| RX_JESD_NP | 16 | --- |
+-------------------+---------------------------+--------------------------+
| TX_JESD_M | 8 | 8 |
+-------------------+---------------------------+--------------------------+
| TX_JESD_L | 4 | 4 |
+-------------------+---------------------------+--------------------------+
| TX_JESD_S | 1 | 1 |
+-------------------+---------------------------+--------------------------+
| TX_JESD_NP | 16 | --- |
+-------------------+---------------------------+--------------------------+
| RX_OS_JESD_M | 0 | --- |
+-------------------+---------------------------+--------------------------+
| RX_OS_JESD_L | 0 | --- |
+-------------------+---------------------------+--------------------------+
| RX_OS_JESD_S | 0 | --- |
+-------------------+---------------------------+--------------------------+
| RX_JESD_NP | 0 | --- |
+-------------------+---------------------------+--------------------------+
+----------------------+------------------------------------------------------+
| Parameter | Default value of the parameters depending on carrier |
+----------------------+---------------------------+--------------------------+
| | ZCU102/VCU118 | A10SoC |
+======================+===========================+==========================+
| JESD_MODE | 8B10B | 8B10B |
+----------------------+---------------------------+--------------------------+
| ORX_ENABLE | 0 | --- |
+----------------------+---------------------------+--------------------------+
| RX_LANE_RATE | 9.83 | 9.83 |
+----------------------+---------------------------+--------------------------+
| TX_LANE_RATE | 9.83 | 9.83 |
+----------------------+---------------------------+--------------------------+
| TX_NUM_LINKS | 1 | 1 |
+----------------------+---------------------------+--------------------------+
| RX_NUM_LINKS | 1 | 1 |
+----------------------+---------------------------+--------------------------+
| RX_OS_NUM_LINKS | 1 | --- |
+----------------------+---------------------------+--------------------------+
| RX_JESD_M | 8 | 8 |
+----------------------+---------------------------+--------------------------+
| RX_JESD_L | 4 | 4 |
+----------------------+---------------------------+--------------------------+
| RX_JESD_S | 1 | 1 |
+----------------------+---------------------------+--------------------------+
| RX_JESD_NP | 16 | --- |
+----------------------+---------------------------+--------------------------+
| RX_JESD_TPL_WIDTH | {} | --- |
+----------------------+---------------------------+--------------------------+
| TX_JESD_M | 8 | 8 |
+----------------------+---------------------------+--------------------------+
| TX_JESD_L | 4 | 4 |
+----------------------+---------------------------+--------------------------+
| TX_JESD_S | 1 | 1 |
+----------------------+---------------------------+--------------------------+
| TX_JESD_NP | 16 | --- |
+----------------------+---------------------------+--------------------------+
| TX_JESD_TPL_WIDTH | {} | --- |
+----------------------+---------------------------+--------------------------+
| RX_OS_JESD_M | 0 | --- |
+----------------------+---------------------------+--------------------------+
| RX_OS_JESD_L | 0 | --- |
+----------------------+---------------------------+--------------------------+
| RX_OS_JESD_S | 0 | --- |
+----------------------+---------------------------+--------------------------+
| RX_OS_JESD_NP | 0 | --- |
+----------------------+---------------------------+--------------------------+
| RX_OS_JESD_TPL_WIDTH | {} | --- |
+----------------------+---------------------------+--------------------------+

A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.

Expand Down Expand Up @@ -747,10 +755,10 @@ following table.
============ ===========================
DAC phy lane FPGA Tx lane / Logical lane
============ ===========================
0 3
1 2
2 0
3 1
0 0
1 1
2 2
3 3
============ ===========================

Resources
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