library/spi_engine: fix inverted interconnect for intel projects #1873
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On intel projects, the s0,s1 connections were inverted before this commit. s1 is intended for the FIFO mode commands and data, and s0 is intended for the Offload mode ones. This inversion meant that when Offload was enabled, the FIFO commands were sent, and vice-versa. Until recently, before #1502, this was relatively benign, and caused only a priority inversion between both the streams. After #1502, however, it makes the offload enable signal behave wrongly, since it's used for selecting between the s0, s1 interfaces. Signed-off-by: Laez Barbosa <[email protected]>
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PIoandan
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Sep 17, 2025
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On intel projects, the s0,s1 connections were inverted before this commit. s1 is intended for the FIFO mode commands and data, and s0 is intended for the Offload mode ones. This inversion meant that when Offload was enabled, the FIFO commands were sent, and vice-versa. Until recently, before #1502, this was relatively benign, and caused only a priority inversion between the two streams. After #1502, however, it makes the offload enable signal behave wrongly, since it's used for selecting between the s0, s1 interfaces. Signed-off-by: Laez Barbosa <[email protected]>
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On intel projects, the s0,s1 connections were inverted before this commit. s1 is intended for the FIFO mode commands and data, and s0 is intended for the Offload mode ones. This inversion meant that when Offload was enabled, the FIFO commands were sent, and vice-versa.
Until recently, before #1502, this was relatively benign, and caused only a priority inversion between both the streams (it would still work, since the interfaces were both active during FIFO and Offload mode). After #1502, however, it makes the offload enable signal behave wrongly, since it's used for selecting between the s0, s1 interfaces.
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