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samd51: DAC: Make clock usage more like Arduino core #2104

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samd51: DAC: Make clock usage more like Arduino core #2104

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4 changes: 2 additions & 2 deletions ports/atmel-samd/asf4_conf/samd51/hpl_dac_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@
// <i> This defines the current in output buffer according to conversion rate
// <id> dac0_arch_cctrl
#ifndef CONF_DAC0_CCTRL
#define CONF_DAC0_CCTRL 1
#define CONF_DAC0_CCTRL 2
#endif

// <q> Run in standby
Expand Down Expand Up @@ -90,7 +90,7 @@
// <i> This defines the current in output buffer according to conversion rate
// <id> dac1_arch_cctrl
#ifndef CONF_DAC1_CCTRL
#define CONF_DAC1_CCTRL 1
#define CONF_DAC1_CCTRL 2
#endif

// <q> Run in standby
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9 changes: 5 additions & 4 deletions ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h
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Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
// Circuit Python SAMD51 clock tree:
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK4, GCLK5
// GCLK1 (48MHz) -> 48 MHz peripherals
// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0, DAC peripherals
// GCLK4 (48MHz divded down to 12MHz) -> DAC
// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0 peripheral
// DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring)

// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,
Expand Down Expand Up @@ -338,7 +339,7 @@
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif

// <q> Run in Standby
Expand Down Expand Up @@ -388,7 +389,7 @@
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#define CONF_GCLK_GEN_4_DIV 4
#endif
// </h>
// </e>
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4 changes: 2 additions & 2 deletions ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -73,15 +73,15 @@
// <id> dac_gclk_selection
// <i> Select the clock source for DAC.
#ifndef CONF_GCLK_DAC_SRC
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK5_Val
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK4_Val
#endif

/**
* \def CONF_GCLK_DAC_FREQUENCY
* \brief DAC's Clock frequency
*/
#ifndef CONF_GCLK_DAC_FREQUENCY
#define CONF_GCLK_DAC_FREQUENCY 2000000
#define CONF_GCLK_DAC_FREQUENCY 12000000
#endif

// <y> EVSYS Channel 0 Clock Source
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4 changes: 2 additions & 2 deletions ports/atmel-samd/common-hal/audioio/AudioOut.c
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Expand Up @@ -198,7 +198,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
#endif
#ifdef SAMD51
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC1M |
DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC12M |
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
Expand All @@ -207,7 +207,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
#ifdef SAMD51
if (channel1_enabled) {
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
DAC->DACCTRL[1].reg = DAC_DACCTRL_CCTRL_CC1M |
DAC->DACCTRL[1].reg = DAC_DACCTRL_CCTRL_CC12M |
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
Expand Down