Possible optimization for unaligned load/store

[chbessonova]

According to MSP430 EABI

• char type should be aligned to 8 bit,
• structures should be aligned to the the most strict alignment requirement among its members.
  So, structures contain chars only will be aligned to 8 bit, which makes all load/stores to that structures unaligned. Unaligned load/stores are performed by 1 byte.

Example:

target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"
target triple = "msp430"

%struct.t = type { i8, i8 }

@T = common local_unnamed_addr global %struct.t zeroinitializer, align 1

define i16 @boo(%struct.t* byval nocapture align 1 %a1) #0 {
entry:
  %0 = bitcast %struct.t* %a1 to i16*
  %1 = load i16, i16* %0, align 1
  store i16 %1, i16* bitcast (%struct.t* @T to i16*), align 1
  ret i16 0
}

llc output:

boo:                                    ; @boo
	sub	#2, r1
	mov.b	1(r12), r13
	add	r13, r13
	mov.b	0(r12), r12
	add	r13, r13
	add	r13, r13
	add	r13, r13
	add	r13, r13
	add	r13, r13
	add	r13, r13
	add	r13, r13
	bis	r12, r13
	mov.b	r13, &T
	mov	r13, 0(r1)
	clrc
	rrc	r13
	rra	r13
	rra	r13
	rra	r13
	rra	r13
	rra	r13
	rra	r13
	rra	r13
	mov.b	r13, &T+1
	clr	r12
	add	#2, r1
	ret

Possible optimizations
Approach 1 (gcc way): Use 16 bit alignment for chars to make all load/stores aligned.

boo:                                    ; @boo
	sub	#2, r1
	mov	0(r12), r12
	mov	r12, 0(r1)
	mov	r12, &T
	clr	r12
	add	#2, r1
	ret

Approach 2 (alternative way): Improve unaligned load/store lowering to use swpb instead of 8 shifts.

[asl]

I would actually implement both.

[chbessonova]

Changing char alignment to 16bit to avoid unaligned loads/stores doesn't look like a good idea to me anymore.
I tested it on newlib and found it increases libc.a size by > 200 bytes.
So, I think it's better to leave aggregates alignment in such cases on the user side.

Moreover, unaligned loads/stores look really better with swpb.