[Issue]: failure of `AMDGPU DAG->DAG Pattern Instruction Selection` due to `llvm.llrint.i64.f32`

[ravil-mobile]

Problem Description

The compiler from ROCm@6.0.2 suite fails to generate the code for llvm.llrint.i64.f32.

Operating System

Ubuntu 20.04.1 LTS

CPU

Intel(R) Xeon(R) Gold 6132 CPU

GPU

AMD Instinct MI100

ROCm Version

ROCm 6.0.0

ROCm Component

llvm-project

Steps to Reproduce

Here is a small reproducible example (func.ll)

declare i64 @llvm.llrint.i64.f32(float)

define i64 @convert(float %arg) {
entry:
  %0 = tail call i64 @llvm.llrint.i64.f32(float %arg)
  ret i64 %0
}

Here is the corresponding Makefile

CC=/opt/rocm/llvm/bin/llc

x86: func.ll
        $(CC) $< -mtriple="x86_64-linux-gnu" -o x86.o

amdgcn: func.ll
        $(CC) $< -mtriple="amdgcn-amd-amdhsa" -o amdgcn.o

clean:
        rm -f x86.o amdgcn.o

Execute the following to reproduce the bug

make amdgcn

(Optional for Linux users) Output of /opt/rocm/bin/rocminfo --support

No response

Additional Information

This bug was discovered during code generation of a Triton kernel. The original source of the issue is here.

[ppanchad-amd]

@ravil-mobile Internal ticket has been created to investigate this issue. Thanks!

[ppanchad-amd]

Fixed:
llvm#98931 - Implement lowering llvm.lrint intrinsic
llvm#98970 - Implement lowering of llvm.lround