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Bug: ports mentioned in verilog file are taken as declaration.

Status: Open.

#135 In PyHDI/Pyverilog;

· rahultanwar10 opened on Jan 30, 2025

Request: Add generated API documentation for this library

Status: Open.

#134 In PyHDI/Pyverilog;

· parker-research opened on Nov 28, 2024

Feature Request: Add strong typing to this library

Status: Open.

#133 In PyHDI/Pyverilog;

· parker-research opened on Nov 28, 2024

TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py

Status: Open.

#131 In PyHDI/Pyverilog;

· zhangshuaiAA9 opened on Jul 13, 2024

ANSI Style localparam causes parsing error

Status: Open.

#129 In PyHDI/Pyverilog;

· mclark-iontra opened on Jun 15, 2024

Codegen arrays

Status: Open.

#128 In PyHDI/Pyverilog;

· CapucinedeBoissac opened on Oct 30, 2023

Unsized numbers without base solution

Status: Open.

#127 In PyHDI/Pyverilog;

· YSJL opened on Oct 30, 2023

parser error

Status: Open.

#126 In PyHDI/Pyverilog;

· 1353369570 opened on Oct 20, 2023

Attribute error in parser

Status: Open.

#125 In PyHDI/Pyverilog;

· KatCe opened on Oct 15, 2023

Parse Error: Cannot parse a function

Status: Open.

#124 In PyHDI/Pyverilog;

· KatCe opened on Oct 15, 2023

AST node

Status: Open.

#122 In PyHDI/Pyverilog;

· lijiale6224 opened on Oct 5, 2023

Can not support "generate case" statement

Status: Open.

#121 In PyHDI/Pyverilog;

· TonyLiaoZP opened on Jun 3, 2023