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Description

The goal of this PR is to add the GCC/ARMClang non-MPU port variant for ARM Cortex-R82 processor ( ARMv8-R AArch64 based ).

This port has the following features:

  • Uses single security state (non TrustZone).
  • Supports SMP (Symmetric multi-processing).
  • Doesn't support Hypervisor (EL2).
  • Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Test Steps

Checklist:

  • I have tested my changes. No regression in existing tests.
  • I have modified and/or added unit-tests to cover the code changes in this Pull Request.

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sonarqubecloud bot commented Jul 9, 2025

@jasonpcarroll
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Hi @AhmedIsmail02,

Apologies for the late response. I will reach out to someone with a bit more familiarity with this architecture (and has a board to test) to take a look.

Best,

Jason Carroll

@AhmedIsmail02
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Hi @jasonpcarroll,

Thanks for getting back to me.

Sure, you can refer them to use the example available here which runs on Arm's FVP.

uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };

/* Flag to control tick ISR handling, this is made true just before schedular start. */
__attribute__( ( section( ".shared_ram" ) ) )
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Why does it need to be placed in shared_ram section?

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That's not needed anymore as the port assumes that the hardware or target model is fully cache coherent. Hence, it's now removed.

AhmedIsmail02 and others added 2 commits September 23, 2025 14:59
The goal of this commit is to add the GCC/ARMClang non-MPU
port variant for ARM Cortex-R82 processor which is
ARMv8-R AArch64 based.
The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port.

This port has the following features:
* Uses single security state (non TrustZone).
* Supports SMP (Symmetric multi-processing).
* Doesn't support Hypervisor (EL2).
* Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Signed-off-by: Ahmed Ismail <[email protected]>
Signed-off-by: Gaurav Aggarwal <[email protected]>
@AhmedIsmail02 AhmedIsmail02 force-pushed the add-cortex-r82-non-mpu-gcc-armclang-port branch from b318112 to afae6d9 Compare September 24, 2025 08:38
This commit includes the following changes

* Currently, the expectation is that applications
would explicitly call xPortStartScheduler() on all
secondary cores. However, this approach places an
unnecessary burden on the application developer and
assumes strict adherence to our example code,
which we cannot guarantee.
To make the port more inclusive and align with the principle
that the kernel should take care of system responsibilities,
we are shifting this logic into the port itself.
With this change, the application developer only needs to call
vTaskStartScheduler() on the primary core, does an SVC call once
the secondary cores are online, and the kernel will ensure
that all secondary cores are properly managed.

* Support tasks running in EL0 and only kernel running in EL1,
the changes are just having multiple SVCs for different purposes
(whenever a privileged instruction (e.g., MSR) is to be executed).

Signed-off-by: Ahmed Ismail <[email protected]>
@AhmedIsmail02 AhmedIsmail02 force-pushed the add-cortex-r82-non-mpu-gcc-armclang-port branch from afae6d9 to 1655021 Compare September 24, 2025 08:46
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codecov bot commented Sep 24, 2025

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 91.46%. Comparing base (386c1bc) to head (1655021).
⚠️ Report is 4 commits behind head on main.

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #1289   +/-   ##
=======================================
  Coverage   91.46%   91.46%           
=======================================
  Files           6        6           
  Lines        3256     3256           
  Branches      899      899           
=======================================
  Hits         2978     2978           
  Misses        132      132           
  Partials      146      146           
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3 participants