Merge pull request #553 from stm32-rs/timer-refac

timer macro/private trait refactoring

Author: burrbull

CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- `timer.rs` refactoring
+
 ## [v0.11.0] - 2025-09-09
 
 ### Breaking changes

src/rcc.rs

@@ -4,7 +4,7 @@ use core::ops::{Deref, DerefMut};
 
 use crate::pac::{
     rcc::{self, RegisterBlock as RccRB},
-    BKP, PWR, RCC,
+    BKP, DBGMCU, PWR, RCC,
 };
 
 use crate::flash::ACR;
@@ -207,6 +207,7 @@ impl Rcc {
     /// let clocks = rcc.freeze(rcc::Config::default(), &mut flash.acr);
     /// ```
     #[inline(always)]
+    #[allow(unused)]
     pub fn freeze(self, cfg: impl Into<RawConfig>, acr: &mut ACR) -> Self {
         let cfg = cfg.into();
         let clocks = cfg.get_clocks();
@@ -544,6 +545,11 @@ pub trait Reset: RccBus {
     }
 }
 
+/// Stop peripheral when Core is halted
+pub trait StopInDebug {
+    fn stop_in_debug(&mut self, dbg: &mut DBGMCU, state: bool);
+}
+
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub struct RawConfig {
     pub hse: Option<u32>,

src/rcc/enable.rs

@@ -54,17 +54,43 @@ macro_rules! bus {
     }
 }
 
+macro_rules! dbgstop {
+    ($($PER:ident => ($bit:literal),)+) => {
+        $(
+            impl StopInDebug for crate::pac::$PER {
+                #[inline(always)]
+                fn stop_in_debug(&mut self, dbg: &mut DBGMCU, state: bool) {
+                    unsafe {
+                        bb::write(dbg.cr(), $bit, state);
+                    }
+                }
+            }
+        )+
+    }
+}
+
 #[cfg(feature = "stm32f103")]
 bus! {
     ADC2 => (APB2, 10),
     CAN => (APB1, 25),
 }
+#[cfg(feature = "stm32f103")]
+dbgstop! {
+    CAN => (14), // dbg_can1_stop
+}
+
 #[cfg(feature = "connectivity")]
 bus! {
     ADC2 => (APB2, 10),
     CAN1 => (APB1, 25),
     CAN2 => (APB1, 26),
 }
+#[cfg(feature = "connectivity")]
+dbgstop! {
+    CAN1 => (14), // dbg_can1_stop
+    CAN2 => (21), // dbg_can2_stop
+}
+
 #[cfg(feature = "has-dac")]
 bus! {
     DAC => (APB1, 29),
@@ -94,6 +120,12 @@ bus! {
     USART3 => (APB1, 18),
     WWDG => (APB1, 11),
 }
+dbgstop! {
+    IWDG => (8), // dbg_iwdg_stop
+    WWDG => (9), // dbg_wwdg_stop
+    I2C1 => (15), // dbg_i2c1_smbus_timeout
+    I2C2 => (16), // dbg_i2c2_smbus_timeout
+}
 
 #[cfg(any(feature = "xl", feature = "high"))]
 bus! {
@@ -130,16 +162,28 @@ bus! {
     TIM2 => (APB1, 0),
     TIM3 => (APB1, 1),
 }
+dbgstop! {
+    TIM2 => (11), // dbg_tim2_stop
+    TIM3 => (12), // dbg_tim3_stop
+}
 
 #[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
 bus! {
     TIM1 => (APB2, 11),
 }
+#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
+dbgstop! {
+    TIM1 => (10), // dbg_tim1_stop
+}
 
 #[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
 bus! {
     TIM6 => (APB1, 4),
 }
+#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
+dbgstop! {
+    TIM6 => (19), // dbg_tim6_stop
+}
 
 #[cfg(any(
     all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
@@ -148,42 +192,79 @@ bus! {
 bus! {
     TIM7 => (APB1, 5),
 }
+#[cfg(any(
+    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
+    any(feature = "stm32f100", feature = "connectivity")
+))]
+dbgstop! {
+    TIM7 => (20), // dbg_tim7_stop
+}
 
 #[cfg(feature = "stm32f100")]
 bus! {
     TIM15 => (APB2, 16),
     TIM16 => (APB2, 17),
     TIM17 => (APB2, 18),
 }
+#[cfg(feature = "stm32f100")]
+dbgstop! {
+    TIM15 => (22), // dbg_tim15_stop
+    TIM16 => (23), // dbg_tim16_stop
+    TIM17 => (24), // dbg_tim17_stop
+}
 
 #[cfg(feature = "medium")]
 bus! {
     TIM4 => (APB1, 2),
 }
+#[cfg(feature = "medium")]
+dbgstop! {
+    TIM4 => (13), // dbg_tim4_stop
+}
 
 #[cfg(any(feature = "high", feature = "connectivity"))]
 bus! {
     TIM5 => (APB1, 3),
 }
+#[cfg(any(feature = "high", feature = "connectivity"))]
+dbgstop! {
+    TIM5 => (18), // dbg_tim5_stop
+}
 
 #[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
 bus! {
     TIM12 => (APB1, 6),
     TIM13 => (APB1, 7),
     TIM14 => (APB1, 8),
 }
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
+dbgstop! {
+    TIM12 => (25), // dbg_tim12_stop
+    TIM13 => (26), // dbg_tim13_stop
+    TIM14 => (27), // dbg_tim14_stop
+}
 
 #[cfg(all(feature = "stm32f103", feature = "high"))]
 bus! {
     TIM8 => (APB2, 13),
 }
+#[cfg(all(feature = "stm32f103", feature = "high"))]
+dbgstop! {
+    TIM8 => (17), // dbg_tim8_stop
+}
 
 #[cfg(feature = "xl")]
 bus! {
     TIM9 => (APB2, 19),
     TIM10 => (APB2, 20),
     TIM11 => (APB2, 21),
 }
+#[cfg(feature = "xl")]
+dbgstop! {
+    TIM9 => (28), // dbg_tim9_stop
+    TIM10 => (29), // dbg_tim10_stop
+    TIM11 => (30), // dbg_tim11_stop
+}
 
 #[cfg(feature = "stm32f103")] // feature = "stm32f102"
 bus! {