move stop_in_debug to independent trait

Author: burrbull

src/rcc.rs

@@ -4,7 +4,7 @@ use core::ops::{Deref, DerefMut};
 
 use crate::pac::{
     rcc::{self, RegisterBlock as RccRB},
-    BKP, PWR, RCC,
+    BKP, DBGMCU, PWR, RCC,
 };
 
 use crate::flash::ACR;
@@ -545,6 +545,11 @@ pub trait Reset: RccBus {
     }
 }
 
+/// Stop peripheral when Core is halted
+pub trait StopInDebug {
+    fn stop_in_debug(&mut self, dbg: &mut DBGMCU, state: bool);
+}
+
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub struct RawConfig {
     pub hse: Option<u32>,

src/rcc/enable.rs

@@ -54,17 +54,43 @@ macro_rules! bus {
     }
 }
 
+macro_rules! dbgstop {
+    ($($PER:ident => ($bit:literal),)+) => {
+        $(
+            impl StopInDebug for crate::pac::$PER {
+                #[inline(always)]
+                fn stop_in_debug(&mut self, dbg: &mut DBGMCU, state: bool) {
+                    unsafe {
+                        bb::write(dbg.cr(), $bit, state);
+                    }
+                }
+            }
+        )+
+    }
+}
+
 #[cfg(feature = "stm32f103")]
 bus! {
     ADC2 => (APB2, 10),
     CAN => (APB1, 25),
 }
+#[cfg(feature = "stm32f103")]
+dbgstop! {
+    CAN => (14), // dbg_can1_stop
+}
+
 #[cfg(feature = "connectivity")]
 bus! {
     ADC2 => (APB2, 10),
     CAN1 => (APB1, 25),
     CAN2 => (APB1, 26),
 }
+#[cfg(feature = "connectivity")]
+dbgstop! {
+    CAN1 => (14), // dbg_can1_stop
+    CAN2 => (21), // dbg_can2_stop
+}
+
 #[cfg(feature = "has-dac")]
 bus! {
     DAC => (APB1, 29),
@@ -94,6 +120,12 @@ bus! {
     USART3 => (APB1, 18),
     WWDG => (APB1, 11),
 }
+dbgstop! {
+    IWDG => (8), // dbg_iwdg_stop
+    WWDG => (9), // dbg_wwdg_stop
+    I2C1 => (15), // dbg_i2c1_smbus_timeout
+    I2C2 => (16), // dbg_i2c2_smbus_timeout
+}
 
 #[cfg(any(feature = "xl", feature = "high"))]
 bus! {
@@ -130,16 +162,28 @@ bus! {
     TIM2 => (APB1, 0),
     TIM3 => (APB1, 1),
 }
+dbgstop! {
+    TIM2 => (11), // dbg_tim2_stop
+    TIM3 => (12), // dbg_tim3_stop
+}
 
 #[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
 bus! {
     TIM1 => (APB2, 11),
 }
+#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
+dbgstop! {
+    TIM1 => (10), // dbg_tim1_stop
+}
 
 #[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
 bus! {
     TIM6 => (APB1, 4),
 }
+#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
+dbgstop! {
+    TIM6 => (19), // dbg_tim6_stop
+}
 
 #[cfg(any(
     all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
@@ -148,42 +192,79 @@ bus! {
 bus! {
     TIM7 => (APB1, 5),
 }
+#[cfg(any(
+    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
+    any(feature = "stm32f100", feature = "connectivity")
+))]
+dbgstop! {
+    TIM7 => (20), // dbg_tim7_stop
+}
 
 #[cfg(feature = "stm32f100")]
 bus! {
     TIM15 => (APB2, 16),
     TIM16 => (APB2, 17),
     TIM17 => (APB2, 18),
 }
+#[cfg(feature = "stm32f100")]
+dbgstop! {
+    TIM15 => (22), // dbg_tim15_stop
+    TIM16 => (23), // dbg_tim16_stop
+    TIM17 => (24), // dbg_tim17_stop
+}
 
 #[cfg(feature = "medium")]
 bus! {
     TIM4 => (APB1, 2),
 }
+#[cfg(feature = "medium")]
+dbgstop! {
+    TIM4 => (13), // dbg_tim4_stop
+}
 
 #[cfg(any(feature = "high", feature = "connectivity"))]
 bus! {
     TIM5 => (APB1, 3),
 }
+#[cfg(any(feature = "high", feature = "connectivity"))]
+dbgstop! {
+    TIM5 => (18), // dbg_tim5_stop
+}
 
 #[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
 bus! {
     TIM12 => (APB1, 6),
     TIM13 => (APB1, 7),
     TIM14 => (APB1, 8),
 }
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
+dbgstop! {
+    TIM12 => (25), // dbg_tim12_stop
+    TIM13 => (26), // dbg_tim13_stop
+    TIM14 => (27), // dbg_tim14_stop
+}
 
 #[cfg(all(feature = "stm32f103", feature = "high"))]
 bus! {
     TIM8 => (APB2, 13),
 }
+#[cfg(all(feature = "stm32f103", feature = "high"))]
+dbgstop! {
+    TIM8 => (17), // dbg_tim8_stop
+}
 
 #[cfg(feature = "xl")]
 bus! {
     TIM9 => (APB2, 19),
     TIM10 => (APB2, 20),
     TIM11 => (APB2, 21),
 }
+#[cfg(feature = "xl")]
+dbgstop! {
+    TIM9 => (28), // dbg_tim9_stop
+    TIM10 => (29), // dbg_tim10_stop
+    TIM11 => (30), // dbg_tim11_stop
+}
 
 #[cfg(feature = "stm32f103")] // feature = "stm32f102"
 bus! {

src/timer.rs

@@ -354,7 +354,7 @@ pub use pac::tim1::cr1::CMS as CenterAlignedMode;
 mod sealed {
     use super::{
         CaptureFilter, CaptureMode, CapturePolarity, CapturePrescaler, CenterAlignedMode, Event,
-        IdleState, Ocm, Polarity, DBG,
+        IdleState, Ocm, Polarity,
     };
     pub trait General {
         type Width: Into<u32> + From<u16>;
@@ -376,7 +376,6 @@ mod sealed {
         fn start_one_pulse(&mut self);
         fn cr1_reset(&mut self);
         fn cnt_reset(&mut self);
-        fn stop_in_debug(&mut self, dbg: &mut DBG, state: bool);
     }
 
     pub trait WithChannel: General {
@@ -422,15 +421,14 @@ mod sealed {
 pub(crate) use sealed::{Advanced, General, MasterTimer, WithCapture, WithChannel, WithPwm};
 
 pub trait Instance:
-    crate::Sealed + rcc::Enable + rcc::Reset + rcc::BusTimerClock + General
+    crate::Sealed + rcc::Enable + rcc::Reset + rcc::BusTimerClock + rcc::StopInDebug + General
 {
 }
 
 macro_rules! hal {
     ($TIM:ty: [
         $Timer:ident,
         $bits:ty,
-        $dbg_timX_stop:ident,
         $(c: ($cnum:tt, $ncnum:tt $(, $aoe:ident)?),)?
         $(m: $timbase:ident,)?
     ]) => {
@@ -529,10 +527,6 @@ macro_rules! hal {
             fn cnt_reset(&mut self) {
                 self.cnt().reset();
             }
-            #[inline(always)]
-            fn stop_in_debug(&mut self, dbg: &mut DBG, state: bool) {
-                dbg.cr().modify(|_, w| w.$dbg_timX_stop().bit(state));
-            }
         }
         $(
             impl WithChannel for $TIM {
@@ -933,62 +927,46 @@ const fn compute_arr_presc(freq: u32, clock: u32) -> (u16, u32) {
 }
 
 #[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
-hal!(pac::TIM1: [Timer1, u16, dbg_tim1_stop, c: (4, 4, _aoe), m: tim1,]);
+hal!(pac::TIM1: [Timer1, u16, c: (4, 4, _aoe), m: tim1,]);
 
-hal!(pac::TIM2: [Timer2, u16, dbg_tim2_stop, c: (4, 0), m: tim2,]);
-hal!(pac::TIM3: [Timer3, u16, dbg_tim3_stop, c: (4, 0), m: tim2,]);
+hal!(pac::TIM2: [Timer2, u16, c: (4, 0), m: tim2,]);
+hal!(pac::TIM3: [Timer3, u16, c: (4, 0), m: tim2,]);
 
 #[cfg(feature = "medium")]
-hal!(pac::TIM4: [Timer4, u16, dbg_tim4_stop, c: (4, 0), m: tim2,]);
+hal!(pac::TIM4: [Timer4, u16, c: (4, 0), m: tim2,]);
 
 #[cfg(any(feature = "high", feature = "connectivity"))]
-hal!(pac::TIM5: [Timer5, u16, dbg_tim5_stop, c: (4, 0), m: tim2,]);
+hal!(pac::TIM5: [Timer5, u16, c: (4, 0), m: tim2,]);
 
 #[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
-hal!(pac::TIM6: [Timer6, u16, dbg_tim6_stop, m: tim6,]);
+hal!(pac::TIM6: [Timer6, u16, m: tim6,]);
 
 #[cfg(any(
     all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
     any(feature = "stm32f100", feature = "connectivity")
 ))]
-hal!(pac::TIM7: [Timer7, u16, dbg_tim7_stop, m: tim6,]);
+hal!(pac::TIM7: [Timer7, u16, m: tim6,]);
 
 #[cfg(all(feature = "stm32f103", feature = "high"))]
-hal!(pac::TIM8: [Timer8, u16, dbg_tim8_stop, c: (4, 4, _aoe), m: tim1,]);
+hal!(pac::TIM8: [Timer8, u16, c: (4, 4, _aoe), m: tim1,]);
 
-//TODO: restore these timers once stm32-rs has been updated
-// dbg_tim(12-13)_stop fields missing from 103 xl in stm32-rs
-// dbg_tim(9-10)_stop fields missing from 101 xl in stm32-rs
-/*
 #[cfg(feature = "xl")]
-hal!(pac::TIM9: [Timer9, u16, dbg_tim9_stop, c: (2, 2),]);
+hal!(pac::TIM9: [Timer9, u16, c: (2, 2),]);
 #[cfg(feature = "xl")]
-hal!(pac::TIM10: [Timer10, u16, dbg_tim10_stop, c: (1, 1),]);
+hal!(pac::TIM10: [Timer10, u16, c: (1, 1),]);
 #[cfg(feature = "xl")]
-hal!(pac::TIM11: [Timer11, u16, dbg_tim11_stop, c: (1, 1),]);
-*/
-#[cfg(any(
-    all(feature = "stm32f100", feature = "high"),
-    all(feature = "stm32f101", feature = "xl"),
-    //all(feature = "stm32f103", feature = "xl"),
-))]
-hal!(pac::TIM12: [Timer12, u16, dbg_tim12_stop, c: (2, 2),]);
-#[cfg(any(
-    all(feature = "stm32f100", feature = "high"),
-    all(feature = "stm32f101", feature = "xl"),
-    //all(feature = "stm32f103", feature = "xl"),
-))]
-hal!(pac::TIM13: [Timer13, u16, dbg_tim13_stop, c: (1, 1),]);
-#[cfg(any(
-    all(feature = "stm32f100", feature = "high"),
-    all(feature = "stm32f101", feature = "xl"),
-    //all(feature = "stm32f103", feature = "xl"),
-))]
-hal!(pac::TIM14: [Timer14, u16, dbg_tim14_stop, c: (1, 1),]);
+hal!(pac::TIM11: [Timer11, u16, c: (1, 1),]);
+
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
+hal!(pac::TIM12: [Timer12, u16, c: (2, 2),]);
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
+hal!(pac::TIM13: [Timer13, u16, c: (1, 1),]);
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
+hal!(pac::TIM14: [Timer14, u16, c: (1, 1),]);
 
 #[cfg(feature = "stm32f100")]
-hal!(pac::TIM15: [Timer15, u16, dbg_tim15_stop, c: (2, 2),]);
+hal!(pac::TIM15: [Timer15, u16, c: (2, 2),]);
 #[cfg(feature = "stm32f100")]
-hal!(pac::TIM16: [Timer16, u16, dbg_tim16_stop, c: (1, 1),]);
+hal!(pac::TIM16: [Timer16, u16, c: (1, 1),]);
 #[cfg(feature = "stm32f100")]
-hal!(pac::TIM17: [Timer17, u16, dbg_tim17_stop, c: (1, 1),]);
+hal!(pac::TIM17: [Timer17, u16, c: (1, 1),]);