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Backport [RISCV] Graduate Zicond to non-experimental (llvm#79811) (llvm#80018)
The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no known correctness issues. Therefore, we should mark support as non-experimental. (cherry-picked from commit d833b9d)
1 parent a2d4a4c commit fe2fca3

18 files changed

+60
-68
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‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Lines changed: 1 addition & 1 deletion
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@@ -39,7 +39,7 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
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// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
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// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
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// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
42-
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
42+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
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// Make sure we append negative features if we override the arch
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// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
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// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 8 additions & 8 deletions
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@@ -764,6 +764,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s
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// CHECK-ZICNTR-EXT: __riscv_zicntr 2000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
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// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izicsr2p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s
@@ -1332,14 +1340,6 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
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// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
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// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zimop0p1 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@ on support follow.
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``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
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``Zicond`` Supported
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``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
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``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
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``Zihintntl`` Supported
@@ -234,9 +235,6 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zicfilp``, ``experimental-zicfiss``
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LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.
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237-
``experimental-zicond``
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LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
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``experimental-ztso``
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LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
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‎llvm/docs/ReleaseNotes.rst

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@@ -181,6 +181,7 @@ Changes to the RISC-V Backend
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specification.
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* The Smepmp 1.0 extension is now supported.
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* ``-mcpu=sifive-p670`` was added.
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* Support for the Zicond extension is no longer experimental.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -128,6 +128,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"zicclsm", {1, 0}},
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{"ziccrse", {1, 0}},
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{"zicntr", {2, 0}},
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{"zicond", {1, 0}},
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{"zicsr", {2, 0}},
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{"zifencei", {2, 0}},
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{"zihintntl", {1, 0}},
@@ -200,8 +201,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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{"zicfilp", {0, 4}},
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{"zicfiss", {0, 4}},
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203-
{"zicond", {1, 0}},
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{"zimop", {0, 1}},
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{"ztso", {0, 1}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -72,7 +72,7 @@ def FeatureStdExtZicntr
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[FeatureStdExtZicsr]>;
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def FeatureStdExtZicond
75-
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
75+
: SubtargetFeature<"zicond", "HasStdExtZicond", "true",
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"'Zicond' (Integer Conditional Operations)">;
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def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
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AssemblerPredicate<(all_of FeatureStdExtZicond),

‎llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

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@@ -8,8 +8,6 @@
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//
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// This file describes the RISC-V instructions from the standard Integer
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// Conditional operations extension (Zicond).
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// This version is still experimental as the 'Zicond' extension hasn't been
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// ratified yet. It is based on v1.0-rc1 of the specification.
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//
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//===----------------------------------------------------------------------===//
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‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -84,7 +84,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
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; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
87-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
87+
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
@@ -186,7 +186,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
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; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
189-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
189+
; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
192192
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s

‎llvm/test/CodeGen/RISCV/cmov-branch-opt.ll

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@@ -3,13 +3,13 @@
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; RUN: | FileCheck -check-prefix=NOCMOV %s
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; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+experimental-zicond -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s
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; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
1010
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \
1111
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
12-
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+experimental-zicond -verify-machineinstrs < %s \
12+
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+zicond -verify-machineinstrs < %s \
1313
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s
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1515
; The conditional move optimization in sifive-p450 requires that only a

‎llvm/test/CodeGen/RISCV/condbinops.ll

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@@ -3,8 +3,8 @@
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; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
6-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
6+
; RUN: llc -mtriple=riscv32 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
7+
; RUN: llc -mtriple=riscv64 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
88

99
define i32 @shl32(i32 %x, i32 %y, i1 %c) {
1010
; RV32I-LABEL: shl32:

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