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cmd/asm, runtime: remove the RSB register from loong64
It was carryover from the mips64 port (where it represented the platform GP register) but LoongArch platform ABI doesn't have the GP concept. Change-Id: Iea326ae13676e95b040b52aaadc08d311b507bd3
1 parent ff6f86a commit ce2b6da

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5 files changed

+8
-13
lines changed

5 files changed

+8
-13
lines changed

src/cmd/asm/internal/arch/arch.go

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,6 @@ func archLoong64(linkArch *obj.LinkArch) *Arch {
536536
// Avoid unintentionally clobbering g using R22.
537537
delete(register, "R22")
538538
register["g"] = loong64.REG_R22
539-
register["RSB"] = loong64.REG_R31
540539
registerPrefix := map[string]bool{
541540
"F": true,
542541
"FCSR": true,

src/cmd/asm/internal/asm/operand_test.go

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -915,8 +915,9 @@ var loong64OperandTests = []operandTest{
915915
{"R27", "R27"},
916916
{"R28", "R28"},
917917
{"R29", "R29"},
918-
{"R30", "R30"},
919918
{"R3", "R3"},
919+
{"R30", "R30"},
920+
{"R31", "R31"},
920921
{"R4", "R4"},
921922
{"R5", "R5"},
922923
{"R6", "R6"},
@@ -925,7 +926,6 @@ var loong64OperandTests = []operandTest{
925926
{"R9", "R9"},
926927
{"a(FP)", "a(FP)"},
927928
{"g", "g"},
928-
{"RSB", "R31"},
929929
{"ret+8(FP)", "ret+8(FP)"},
930930
{"runtime·abort(SB)", "runtime.abort(SB)"},
931931
{"·AddUint32(SB)", "\"\".AddUint32(SB)"},

src/runtime/mkpreempt.go

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -462,20 +462,18 @@ func genLoong64() {
462462
movf := "MOVD"
463463
add := "ADDV"
464464
sub := "SUBV"
465-
r31 := "RSB"
466465
regsize := 8
467466

468467
// Add integer registers r4-r21 r23-r29 r31
469468
// R0 (zero), R30 (REGTMP), R2 (tp), R3 (SP), R22 (g), R1 (LR) are special,
470469
var l = layout{sp: "R3", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
471-
for i := 4; i <= 29; i++ {
472-
if i == 22 {
473-
continue // R3 is REGSP R22 is g
470+
for i := 4; i <= 31; i++ {
471+
if i == 22 || i == 30 {
472+
continue
474473
}
475474
reg := fmt.Sprintf("R%d", i)
476475
l.add(mov, reg, regsize)
477476
}
478-
l.add(mov, r31, regsize)
479477

480478
// Add floating point registers F0-F31.
481479
for i := 0; i <= 31; i++ {

src/runtime/preempt_loong64.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
3131
MOVV R27, 184(R3)
3232
MOVV R28, 192(R3)
3333
MOVV R29, 200(R3)
34-
MOVV RSB, 208(R3)
34+
MOVV R31, 208(R3)
3535
MOVD F0, 216(R3)
3636
MOVD F1, 224(R3)
3737
MOVD F2, 232(R3)
@@ -97,7 +97,7 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
9797
MOVD 232(R3), F2
9898
MOVD 224(R3), F1
9999
MOVD 216(R3), F0
100-
MOVV 208(R3), RSB
100+
MOVV 208(R3), R31
101101
MOVV 200(R3), R29
102102
MOVV 192(R3), R28
103103
MOVV 184(R3), R27

src/runtime/signal_loong64.go

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -77,10 +77,8 @@ func (c *sigctxt) preparePanic(sig uint32, gp *g) {
7777
}
7878

7979
// In case we are panicking from external C code
80-
sigpanicPC := uint64(abi.FuncPCABIInternal(sigpanic))
81-
c.set_r31(sigpanicPC >> 32 << 32) // RSB register
8280
c.set_r22(uint64(uintptr(unsafe.Pointer(gp))))
83-
c.set_pc(sigpanicPC)
81+
c.set_pc(uint64(abi.FuncPCABIInternal(sigpanic)))
8482
}
8583

8684
func (c *sigctxt) pushCall(targetPC, resumePC uintptr) {

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