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[X86][CodeGen] Add base atan2 intrinsic lowering (p4)
This change is part of this proposal: https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294 Based on example PR llvm#96222 and fix PR llvm#101268, with some differences due to 2-arg intrinsic and intermediate refactor (RuntimeLibCalls.cpp). - Add llvm.experimental.constrained.atan2 - Intrinsics.td, ConstrainedOps.def, LangRef.rst - Add to ISDOpcodes.h and TargetSelectionDAG.td, connect to intrinsic in BasicTTIImpl.h, and LibFunc_ in SelectionDAGBuilder.cpp, and map generic op in SelectionDAGCompat.td - Update LegalizeDAG.cpp, LegalizeFloatTypes.cpp, LegalizeVectorOps.cpp, and LegalizeVectorTypes.cpp - Update isKnownNeverNaN in SelectionDAG.cpp - Update SelectionDAGDumper.cpp - Update libcalls - RuntimeLibcalls.def, RuntimeLibcalls.cpp, LegalizerHelper.cpp - Update isKnownNeverNaN for generic opcode in GlobalISel/Utils.cpp - TargetLoweringBase.cpp - Expand for vectors, promote f16 - X86ISelLowering.cpp - Expand f80, promote f32 to f64 for MSVC
1 parent b70d327 commit db0ae9c

27 files changed

+594
-5
lines changed

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1993,6 +1993,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
19931993
case Intrinsic::atan:
19941994
ISD = ISD::FATAN;
19951995
break;
1996+
case Intrinsic::atan2:
1997+
ISD = ISD::FATAN2;
1998+
break;
19961999
case Intrinsic::sinh:
19972000
ISD = ISD::FSINH;
19982001
break;

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -425,6 +425,7 @@ enum NodeType {
425425
STRICT_FASIN,
426426
STRICT_FACOS,
427427
STRICT_FATAN,
428+
STRICT_FATAN2,
428429
STRICT_FSINH,
429430
STRICT_FCOSH,
430431
STRICT_FTANH,
@@ -994,6 +995,8 @@ enum NodeType {
994995
FPOWI,
995996
/// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
996997
FLDEXP,
998+
/// FATAN2 - atan2, inspired by libm.
999+
FATAN2,
9971000

9981001
/// FFREXP - frexp, extract fractional and exponent component of a
9991002
/// floating-point value. Returns the two components as separate return

‎llvm/include/llvm/IR/ConstrainedOps.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ CMP_INSTRUCTION(FCmp, 2, 0, experimental_constrained_fcmps, FSETCCS
7272
DAG_FUNCTION(acos, 1, 1, experimental_constrained_acos, FACOS)
7373
DAG_FUNCTION(asin, 1, 1, experimental_constrained_asin, FASIN)
7474
DAG_FUNCTION(atan, 1, 1, experimental_constrained_atan, FATAN)
75+
DAG_FUNCTION(atan2, 2, 1, experimental_constrained_atan2, FATAN2)
7576
DAG_FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
7677
DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
7778
DAG_FUNCTION(cosh, 1, 1, experimental_constrained_cosh, FCOSH)

‎llvm/include/llvm/IR/Intrinsics.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1226,6 +1226,11 @@ let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn, IntrStrictFP] in
12261226
[ LLVMMatchType<0>,
12271227
llvm_metadata_ty,
12281228
llvm_metadata_ty ]>;
1229+
def int_experimental_constrained_atan2 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
1230+
[ LLVMMatchType<0>,
1231+
LLVMMatchType<0>,
1232+
llvm_metadata_ty,
1233+
llvm_metadata_ty ]>;
12291234
def int_experimental_constrained_sin : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
12301235
[ LLVMMatchType<0>,
12311236
llvm_metadata_ty,

‎llvm/include/llvm/IR/RuntimeLibcalls.def

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -232,6 +232,11 @@ HANDLE_LIBCALL(ATAN_F64, "atan")
232232
HANDLE_LIBCALL(ATAN_F80, "atanl")
233233
HANDLE_LIBCALL(ATAN_F128,"atanl")
234234
HANDLE_LIBCALL(ATAN_PPCF128, "atanl")
235+
HANDLE_LIBCALL(ATAN2_F32, "atan2f")
236+
HANDLE_LIBCALL(ATAN2_F64, "atan2")
237+
HANDLE_LIBCALL(ATAN2_F80, "atan2l")
238+
HANDLE_LIBCALL(ATAN2_F128,"atan2l")
239+
HANDLE_LIBCALL(ATAN2_PPCF128, "atan2l")
235240
HANDLE_LIBCALL(SINCOS_F32, nullptr)
236241
HANDLE_LIBCALL(SINCOS_F64, nullptr)
237242
HANDLE_LIBCALL(SINCOS_F80, nullptr)

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ def : GINodeEquiv<G_FTAN, ftan>;
154154
def : GINodeEquiv<G_FACOS, facos>;
155155
def : GINodeEquiv<G_FASIN, fasin>;
156156
def : GINodeEquiv<G_FATAN, fatan>;
157+
def : GINodeEquiv<G_FATAN2, fatan2>;
157158
def : GINodeEquiv<G_FCOSH, fcosh>;
158159
def : GINodeEquiv<G_FSINH, fsinh>;
159160
def : GINodeEquiv<G_FTANH, ftanh>;

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -534,6 +534,7 @@ def ftan : SDNode<"ISD::FTAN" , SDTFPUnaryOp>;
534534
def fasin : SDNode<"ISD::FASIN" , SDTFPUnaryOp>;
535535
def facos : SDNode<"ISD::FACOS" , SDTFPUnaryOp>;
536536
def fatan : SDNode<"ISD::FATAN" , SDTFPUnaryOp>;
537+
def fatan2 : SDNode<"ISD::FATAN2" , SDTFPBinOp>;
537538
def fsinh : SDNode<"ISD::FSINH" , SDTFPUnaryOp>;
538539
def fcosh : SDNode<"ISD::FCOSH" , SDTFPUnaryOp>;
539540
def ftanh : SDNode<"ISD::FTANH" , SDTFPUnaryOp>;
@@ -602,6 +603,8 @@ def strict_facos : SDNode<"ISD::STRICT_FACOS",
602603
SDTFPUnaryOp, [SDNPHasChain]>;
603604
def strict_fatan : SDNode<"ISD::STRICT_FATAN",
604605
SDTFPUnaryOp, [SDNPHasChain]>;
606+
def strict_fatan2 : SDNode<"ISD::STRICT_FATAN2",
607+
SDTFPBinOp, [SDNPHasChain]>;
605608
def strict_fsinh : SDNode<"ISD::STRICT_FSINH",
606609
SDTFPUnaryOp, [SDNPHasChain]>;
607610
def strict_fcosh : SDNode<"ISD::STRICT_FCOSH",
@@ -1588,6 +1591,9 @@ def any_facos : PatFrags<(ops node:$src),
15881591
def any_fatan : PatFrags<(ops node:$src),
15891592
[(strict_fatan node:$src),
15901593
(fatan node:$src)]>;
1594+
def any_fatan2 : PatFrags<(ops node:$src1, node:$src2),
1595+
[(strict_fatan2 node:$src1, node:$src2),
1596+
(fatan2 node:$src1, node:$src2)]>;
15911597
def any_fsinh : PatFrags<(ops node:$src),
15921598
[(strict_fsinh node:$src),
15931599
(fsinh node:$src)]>;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -457,6 +457,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
457457
RTLIBCASE(ACOS_F);
458458
case TargetOpcode::G_FATAN:
459459
RTLIBCASE(ATAN_F);
460+
case TargetOpcode::G_FATAN2:
461+
RTLIBCASE(ATAN2_F);
460462
case TargetOpcode::G_FSINH:
461463
RTLIBCASE(SINH_F);
462464
case TargetOpcode::G_FCOSH:
@@ -1202,6 +1204,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
12021204
case TargetOpcode::G_FACOS:
12031205
case TargetOpcode::G_FASIN:
12041206
case TargetOpcode::G_FATAN:
1207+
case TargetOpcode::G_FATAN2:
12051208
case TargetOpcode::G_FCOSH:
12061209
case TargetOpcode::G_FSINH:
12071210
case TargetOpcode::G_FTANH:
@@ -3122,6 +3125,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
31223125
case TargetOpcode::G_FACOS:
31233126
case TargetOpcode::G_FASIN:
31243127
case TargetOpcode::G_FATAN:
3128+
case TargetOpcode::G_FATAN2:
31253129
case TargetOpcode::G_FCOSH:
31263130
case TargetOpcode::G_FSINH:
31273131
case TargetOpcode::G_FTANH:

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,7 @@ bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
828828
case TargetOpcode::G_FACOS:
829829
case TargetOpcode::G_FASIN:
830830
case TargetOpcode::G_FATAN:
831+
case TargetOpcode::G_FATAN2:
831832
case TargetOpcode::G_FCOSH:
832833
case TargetOpcode::G_FSINH:
833834
case TargetOpcode::G_FTANH:
@@ -1715,6 +1716,7 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17151716
case TargetOpcode::G_FACOS:
17161717
case TargetOpcode::G_FASIN:
17171718
case TargetOpcode::G_FATAN:
1719+
case TargetOpcode::G_FATAN2:
17181720
case TargetOpcode::G_FCOSH:
17191721
case TargetOpcode::G_FSINH:
17201722
case TargetOpcode::G_FTANH:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4599,6 +4599,11 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
45994599
ExpandFPLibCall(Node, RTLIB::ATAN_F32, RTLIB::ATAN_F64, RTLIB::ATAN_F80,
46004600
RTLIB::ATAN_F128, RTLIB::ATAN_PPCF128, Results);
46014601
break;
4602+
case ISD::FATAN2:
4603+
case ISD::STRICT_FATAN2:
4604+
ExpandFPLibCall(Node, RTLIB::ATAN2_F32, RTLIB::ATAN2_F64, RTLIB::ATAN2_F80,
4605+
RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128, Results);
4606+
break;
46024607
case ISD::FSINH:
46034608
case ISD::STRICT_FSINH:
46044609
ExpandFPLibCall(Node, RTLIB::SINH_F32, RTLIB::SINH_F64, RTLIB::SINH_F80,
@@ -5485,6 +5490,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54855490
case ISD::FMINIMUMNUM:
54865491
case ISD::FMAXIMUMNUM:
54875492
case ISD::FPOW:
5493+
case ISD::FATAN2:
54885494
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
54895495
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
54905496
Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
@@ -5501,6 +5507,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
55015507
case ISD::STRICT_FMAXNUM:
55025508
case ISD::STRICT_FREM:
55035509
case ISD::STRICT_FPOW:
5510+
case ISD::STRICT_FATAN2:
55045511
Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
55055512
{Node->getOperand(0), Node->getOperand(1)});
55065513
Tmp2 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
8484
case ISD::FASIN: R = SoftenFloatRes_FASIN(N); break;
8585
case ISD::STRICT_FATAN:
8686
case ISD::FATAN: R = SoftenFloatRes_FATAN(N); break;
87+
case ISD::STRICT_FATAN2:
88+
case ISD::FATAN2: R = SoftenFloatRes_FATAN2(N); break;
8789
case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break;
8890
case ISD::STRICT_FCEIL:
8991
case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
@@ -366,6 +368,13 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FATAN(SDNode *N) {
366368
RTLIB::ATAN_F80, RTLIB::ATAN_F128, RTLIB::ATAN_PPCF128));
367369
}
368370

371+
SDValue DAGTypeLegalizer::SoftenFloatRes_FATAN2(SDNode *N) {
372+
return SoftenFloatRes_Binary(
373+
N,
374+
GetFPLibCall(N->getValueType(0), RTLIB::ATAN2_F32, RTLIB::ATAN2_F64,
375+
RTLIB::ATAN2_F80, RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128));
376+
}
377+
369378
SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
370379
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
371380
RTLIB::CBRT_F32,
@@ -1430,6 +1439,8 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
14301439
case ISD::FASIN: ExpandFloatRes_FASIN(N, Lo, Hi); break;
14311440
case ISD::STRICT_FATAN:
14321441
case ISD::FATAN: ExpandFloatRes_FATAN(N, Lo, Hi); break;
1442+
case ISD::STRICT_FATAN2:
1443+
case ISD::FATAN2: ExpandFloatRes_FATAN2(N, Lo, Hi); break;
14331444
case ISD::FCBRT: ExpandFloatRes_FCBRT(N, Lo, Hi); break;
14341445
case ISD::STRICT_FCEIL:
14351446
case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
@@ -1631,6 +1642,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FATAN(SDNode *N, SDValue &Lo,
16311642
Lo, Hi);
16321643
}
16331644

1645+
void DAGTypeLegalizer::ExpandFloatRes_FATAN2(SDNode *N, SDValue &Lo,
1646+
SDValue &Hi) {
1647+
ExpandFloatRes_Binary(N,
1648+
GetFPLibCall(N->getValueType(0), RTLIB::ATAN2_F32,
1649+
RTLIB::ATAN2_F64, RTLIB::ATAN2_F80,
1650+
RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128),
1651+
Lo, Hi);
1652+
}
1653+
16341654
void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
16351655
SDValue &Hi) {
16361656
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CBRT_F32,
@@ -2673,6 +2693,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
26732693
case ISD::FMINNUM_IEEE:
26742694
case ISD::FMUL:
26752695
case ISD::FPOW:
2696+
case ISD::FATAN2:
26762697
case ISD::FREM:
26772698
case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
26782699

@@ -3115,6 +3136,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
31153136
case ISD::FMINNUM:
31163137
case ISD::FMUL:
31173138
case ISD::FPOW:
3139+
case ISD::FATAN2:
31183140
case ISD::FREM:
31193141
case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break;
31203142

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -567,6 +567,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
567567
SDValue SoftenFloatRes_FACOS(SDNode *N);
568568
SDValue SoftenFloatRes_FASIN(SDNode *N);
569569
SDValue SoftenFloatRes_FATAN(SDNode *N);
570+
SDValue SoftenFloatRes_FATAN2(SDNode *N);
570571
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
571572
SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
572573
SDValue SoftenFloatRes_FMINIMUMNUM(SDNode *N);
@@ -661,6 +662,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
661662
void ExpandFloatRes_FACOS (SDNode *N, SDValue &Lo, SDValue &Hi);
662663
void ExpandFloatRes_FASIN (SDNode *N, SDValue &Lo, SDValue &Hi);
663664
void ExpandFloatRes_FATAN (SDNode *N, SDValue &Lo, SDValue &Hi);
665+
void ExpandFloatRes_FATAN2 (SDNode *N, SDValue &Lo, SDValue &Hi);
664666
void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
665667
void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
666668
void ExpandFloatRes_FMINIMUMNUM(SDNode *N, SDValue &Lo, SDValue &Hi);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
410410
case ISD::FASIN:
411411
case ISD::FACOS:
412412
case ISD::FATAN:
413+
case ISD::FATAN2:
413414
case ISD::FSINH:
414415
case ISD::FCOSH:
415416
case ISD::FTANH:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
164164
case ISD::USHLSAT:
165165

166166
case ISD::FPOW:
167+
case ISD::FATAN2:
167168
case ISD::FREM:
168169
case ISD::FSUB:
169170
case ISD::MUL:
@@ -1291,6 +1292,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
12911292
case ISD::UDIV: case ISD::VP_UDIV:
12921293
case ISD::FDIV: case ISD::VP_FDIV:
12931294
case ISD::FPOW:
1295+
case ISD::FATAN2:
12941296
case ISD::AND: case ISD::VP_AND:
12951297
case ISD::OR: case ISD::VP_OR:
12961298
case ISD::XOR: case ISD::VP_XOR:
@@ -4579,6 +4581,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45794581
break;
45804582

45814583
case ISD::FPOW:
4584+
case ISD::FATAN2:
45824585
case ISD::FREM:
45834586
if (unrollExpandedOp())
45844587
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5460,6 +5460,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
54605460
case ISD::FASIN:
54615461
case ISD::FACOS:
54625462
case ISD::FATAN:
5463+
case ISD::FATAN2:
54635464
case ISD::FSINH:
54645465
case ISD::FCOSH:
54655466
case ISD::FTANH:

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6850,6 +6850,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
68506850
getValue(I.getArgOperand(0)), Flags));
68516851
return;
68526852
}
6853+
case Intrinsic::atan2:
6854+
setValue(&I, DAG.getNode(ISD::FATAN2, sdl,
6855+
getValue(I.getArgOperand(0)).getValueType(),
6856+
getValue(I.getArgOperand(0)),
6857+
getValue(I.getArgOperand(1)), Flags));
6858+
return;
68536859
case Intrinsic::lround:
68546860
case Intrinsic::llround:
68556861
case Intrinsic::lrint:
@@ -9342,6 +9348,12 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
93429348
if (visitUnaryFloatCall(I, ISD::FATAN))
93439349
return;
93449350
break;
9351+
case LibFunc_atan2:
9352+
case LibFunc_atan2f:
9353+
case LibFunc_atan2l:
9354+
if (visitBinaryFloatCall(I, ISD::FATAN2))
9355+
return;
9356+
break;
93459357
case LibFunc_sinh:
93469358
case LibFunc_sinhf:
93479359
case LibFunc_sinhl:

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -227,6 +227,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
227227
case ISD::STRICT_FACOS: return "strict_facos";
228228
case ISD::FATAN: return "fatan";
229229
case ISD::STRICT_FATAN: return "strict_fatan";
230+
case ISD::FATAN2: return "fatan2";
231+
case ISD::STRICT_FATAN2: return "strict_fatan2";
230232
case ISD::FSINH: return "fsinh";
231233
case ISD::STRICT_FSINH: return "strict_fsinh";
232234
case ISD::FCOSH: return "fcosh";

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,7 @@ void TargetLoweringBase::initActions() {
783783
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
784784
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
785785
ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
786-
ISD::FCOSH, ISD::FSINH, ISD::FTANH},
786+
ISD::FCOSH, ISD::FSINH, ISD::FTANH, ISD::FATAN2},
787787
VT, Expand);
788788

789789
// Constrained floating-point operations default to expand.
@@ -842,15 +842,16 @@ void TargetLoweringBase::initActions() {
842842
ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
843843
ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
844844
ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
845-
ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
845+
ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH,
846+
ISD::FATAN2},
846847
{MVT::f32, MVT::f64, MVT::f128}, Expand);
847848

848849
// FIXME: Query RuntimeLibCalls to make the decision.
849850
setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
850851
{MVT::f32, MVT::f64, MVT::f128}, LibCall);
851852

852853
setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
853-
ISD::FSINH, ISD::FTANH},
854+
ISD::FSINH, ISD::FTANH, ISD::FATAN2},
854855
MVT::f16, Promote);
855856
// Default ISD::TRAP to expand (which turns it into abort).
856857
setOperationAction(ISD::TRAP, MVT::Other, Expand);

‎llvm/lib/IR/RuntimeLibcalls.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
4949
setLibcallName(RTLIB::ASIN_F128, "asinf128");
5050
setLibcallName(RTLIB::ACOS_F128, "acosf128");
5151
setLibcallName(RTLIB::ATAN_F128, "atanf128");
52+
setLibcallName(RTLIB::ATAN2_F128, "atan2f128");
5253
setLibcallName(RTLIB::SINH_F128, "sinhf128");
5354
setLibcallName(RTLIB::COSH_F128, "coshf128");
5455
setLibcallName(RTLIB::TANH_F128, "tanhf128");

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -858,6 +858,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
858858
setOperationAction(ISD::FASIN , MVT::f80, Expand);
859859
setOperationAction(ISD::FACOS , MVT::f80, Expand);
860860
setOperationAction(ISD::FATAN , MVT::f80, Expand);
861+
setOperationAction(ISD::FATAN2 , MVT::f80, Expand);
861862
setOperationAction(ISD::FSINH , MVT::f80, Expand);
862863
setOperationAction(ISD::FCOSH , MVT::f80, Expand);
863864
setOperationAction(ISD::FTANH , MVT::f80, Expand);
@@ -2562,6 +2563,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
25622563
{ISD::FACOS, ISD::STRICT_FACOS,
25632564
ISD::FASIN, ISD::STRICT_FASIN,
25642565
ISD::FATAN, ISD::STRICT_FATAN,
2566+
ISD::FATAN2, ISD::STRICT_FATAN2,
25652567
ISD::FCEIL, ISD::STRICT_FCEIL,
25662568
ISD::FCOS, ISD::STRICT_FCOS,
25672569
ISD::FCOSH, ISD::STRICT_FCOSH,

‎llvm/test/Assembler/fp-intrinsics-attr.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,11 @@ define void @func(double %a, double %b, double %c, i32 %i) strictfp {
105105
metadata !"round.dynamic",
106106
metadata !"fpexcept.strict")
107107

108+
%atan2 = call double @llvm.experimental.constrained.atan2.f64(
109+
double %a, double %b,
110+
metadata !"round.dynamic",
111+
metadata !"fpexcept.strict")
112+
108113
%cosh = call double @llvm.experimental.constrained.cosh.f64(
109114
double %a,
110115
metadata !"round.dynamic",
@@ -291,6 +296,9 @@ declare double @llvm.experimental.constrained.acos.f64(double, metadata, metadat
291296
declare double @llvm.experimental.constrained.atan.f64(double, metadata, metadata)
292297
; CHECK: @llvm.experimental.constrained.atan.f64({{.*}}) #[[ATTR1]]
293298

299+
declare double @llvm.experimental.constrained.atan2.f64(double, double, metadata, metadata)
300+
; CHECK: @llvm.experimental.constrained.atan2.f64({{.*}}) #[[ATTR1]]
301+
294302
declare double @llvm.experimental.constrained.sinh.f64(double, metadata, metadata)
295303
; CHECK: @llvm.experimental.constrained.sinh.f64({{.*}}) #[[ATTR1]]
296304

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