Implement environment call properly

Implement ecall instruction with control and status
registers (CSRs).

However, there may occur the situation that the elf
file doesn't contain any csr instruction. It will make
pc point to wrong address.

To resolve this, using 0 as the initial value of mtvec.
By default, the emulator executes default exception
handler when an exception occurs and mtvec stores 0.

Author: Risheng1128

README.md

@@ -84,10 +84,7 @@ Current progress of this emulator in riscv-arch-test(RV32):
     - `M`: Standard Extension for Integer Multiplication and Division
     - `C`: Standard Extension for Compressed Instruction
     - `Zifencei`: Instruction-Fetch Fence
-* Failed Tests
     - `privilege`: RISCV Privileged Specification
-        + 1 system calls
-            * `ecall`
 * Unsupported tests (runnable but incomplete)
     - `F` Standard Extension for Single-Precision Floating-Point
 

src/emulate.c

@@ -40,14 +40,25 @@ extern struct target_ops gdbstub_ops;
     _(breakpoint)       /* Breakpoint */                     \
     _(load_misaligned)  /* Load address misaligned */        \
     _(load_fault)       /* Load access fault */              \
-    _(store_misaligned) /* Store/AMO address misaligned */
+    _(store_misaligned) /* Store/AMO address misaligned */   \
+    _(store_fault)      /* Store/AMO access fault */         \
+    _(ecall_U)          /* Environment call from U-mode */   \
+    _(ecall_S)          /* Environment call from S-mode */   \
+    _(reserved)         /* Reserved */                       \
+    _(ecall_M)          /* Environment call from M-mode */
 
 enum {
 #define _(type) GET_EXCEPTION_CODE(type),
     RV_EXCEPTION_LIST
 #undef _
 };
 
+static void rv_exception_default_handler(struct riscv_t *rv)
+{
+    rv->csr_mepc += rv->insn_len;
+    rv->PC = rv->csr_mepc; /* mret */
+}
+
 #define EXCEPTION_HANDLER_IMPL(type)                                        \
     UNUSED static void rv_except_##type(struct riscv_t *rv, uint32_t mtval) \
     {                                                                       \
@@ -61,9 +72,15 @@ enum {
         const uint32_t code = GET_EXCEPTION_CODE(type);                     \
         /* mepc  (Machine Exception Program Counter)                        \
          * mtval (Machine Trap Value Register)                              \
+         * mcause (Machine Cause Register): store exception code            \
          */                                                                 \
         rv->csr_mepc = rv->PC;                                              \
         rv->csr_mtval = mtval;                                              \
+        rv->csr_mcause = code;                                              \
+        if (!rv->csr_mtvec) { /* elf doesn't implement csr instruction */   \
+            rv_exception_default_handler(rv);                               \
+            return;                                                         \
+        }                                                                   \
         switch (mode) {                                                     \
         case 0: /* DIRECT: All exceptions set PC to base */                 \
             rv->PC = base;                                                  \
@@ -73,8 +90,6 @@ enum {
             rv->PC = base + 4 * code;                                       \
             break;                                                          \
         }                                                                   \
-        /* mcause (Machine Cause Register): store exception code */         \
-        rv->csr_mcause = code;                                              \
     }
 
 /* RISC-V exception handlers */
@@ -775,7 +790,7 @@ static inline bool op_system(struct riscv_t *rv, uint32_t insn)
         switch (funct12) { /* dispatch from imm field */
         case 0:            /* ECALL: Environment Call */
             rv->io.on_ecall(rv);
-            break;
+            return true;
         case 1: /* EBREAK: Environment Break */
             rv->io.on_ebreak(rv);
             return true;
@@ -2118,6 +2133,7 @@ void rv_reset(struct riscv_t *rv, riscv_word_t pc)
     rv->X[rv_reg_sp] = DEFAULT_STACK_ADDR;
 
     /* reset the csrs */
+    rv->csr_mtvec = 0;
     rv->csr_cycle = 0;
     rv->csr_mstatus = 0;
 
@@ -2141,3 +2157,10 @@ void ebreak_handler(struct riscv_t *rv)
     assert(rv);
     rv_except_breakpoint(rv, rv->PC);
 }
+
+void ecall_handler(struct riscv_t *rv)
+{
+    assert(rv);
+    rv_except_ecall_M(rv, 0);
+    syscall_handler(rv);
+}

src/main.c

@@ -199,7 +199,7 @@ int main(int argc, char **args)
         .mem_write_b = MEMIO(write_b),
 
         /* system */
-        .on_ecall = syscall_handler,
+        .on_ecall = ecall_handler,
         .on_ebreak = ebreak_handler,
     };
 

src/riscv.h

@@ -130,6 +130,9 @@ riscv_word_t rv_get_reg(struct riscv_t *, uint32_t reg);
 /* system call handler */
 void syscall_handler(struct riscv_t *rv);
 
+/* environment call handler */
+void ecall_handler(struct riscv_t *rv);
+
 /* breakpoint exception handler */
 void ebreak_handler(struct riscv_t *rv);
 

src/syscall.c

@@ -336,7 +336,6 @@ void syscall_handler(struct riscv_t *rv)
 #undef _
     default:
         fprintf(stderr, "unknown syscall %d\n", (int) syscall);
-        rv_halt(rv);
         break;
     }
 }