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jservjserv
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Merge pull request #530 from RinHizakura/debug-mode-optimize
Use instruction-based emulation for debug mode
2 parents f7fd15b + ecb20c8 commit d8bf69a

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4 files changed

+127
-81
lines changed

4 files changed

+127
-81
lines changed

‎src/emulate.c‎

Lines changed: 76 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -862,12 +862,9 @@ static block_t *block_find_or_translate(riscv_t *rv)
862862
block_translate(rv, next_blk);
863863

864864
optimize_constant(rv, next_blk);
865-
#if RV32_HAS(GDBSTUB)
866-
if (likely(!rv->debug_mode))
867-
#endif
868865
#if RV32_HAS(MOP_FUSION)
869-
/* macro operation fusion */
870-
match_pattern(rv, next_blk);
866+
/* macro operation fusion */
867+
match_pattern(rv, next_blk);
871868
#endif
872869

873870
#if !RV32_HAS(JIT)
@@ -958,6 +955,41 @@ static bool rv_has_plic_trap(riscv_t *rv)
958955
return ((rv->csr_sstatus & SSTATUS_SIE || !rv->priv_mode) &&
959956
(rv->csr_sip & rv->csr_sie));
960957
}
958+
959+
static void rv_check_interrupt(riscv_t *rv)
960+
{
961+
vm_attr_t *attr = PRIV(rv);
962+
if (peripheral_update_ctr-- == 0) {
963+
peripheral_update_ctr = 64;
964+
965+
u8250_check_ready(PRIV(rv)->uart);
966+
if (PRIV(rv)->uart->in_ready)
967+
emu_update_uart_interrupts(rv);
968+
}
969+
970+
if (ctr > attr->timer)
971+
rv->csr_sip |= RV_INT_STI;
972+
else
973+
rv->csr_sip &= ~RV_INT_STI;
974+
975+
if (rv_has_plic_trap(rv)) {
976+
uint32_t intr_applicable = rv->csr_sip & rv->csr_sie;
977+
uint8_t intr_idx = ilog2(intr_applicable);
978+
switch (intr_idx) {
979+
case (SUPERVISOR_SW_INTR & 0xf):
980+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_SW_INTR, 0);
981+
break;
982+
case (SUPERVISOR_TIMER_INTR & 0xf):
983+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_TIMER_INTR, 0);
984+
break;
985+
case (SUPERVISOR_EXTERNAL_INTR & 0xf):
986+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_EXTERNAL_INTR, 0);
987+
break;
988+
default:
989+
break;
990+
}
991+
}
992+
}
961993
#endif
962994

963995
void rv_step(void *arg)
@@ -975,38 +1007,8 @@ void rv_step(void *arg)
9751007
while (rv->csr_cycle < cycles_target && !rv->halt) {
9761008
#if RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER)
9771009
/* check for any interrupt after every block emulation */
978-
979-
if (peripheral_update_ctr-- == 0) {
980-
peripheral_update_ctr = 64;
981-
982-
u8250_check_ready(PRIV(rv)->uart);
983-
if (PRIV(rv)->uart->in_ready)
984-
emu_update_uart_interrupts(rv);
985-
}
986-
987-
if (ctr > attr->timer)
988-
rv->csr_sip |= RV_INT_STI;
989-
else
990-
rv->csr_sip &= ~RV_INT_STI;
991-
992-
if (rv_has_plic_trap(rv)) {
993-
uint32_t intr_applicable = rv->csr_sip & rv->csr_sie;
994-
uint8_t intr_idx = ilog2(intr_applicable);
995-
switch (intr_idx) {
996-
case (SUPERVISOR_SW_INTR & 0xf):
997-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_SW_INTR, 0);
998-
break;
999-
case (SUPERVISOR_TIMER_INTR & 0xf):
1000-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_TIMER_INTR, 0);
1001-
break;
1002-
case (SUPERVISOR_EXTERNAL_INTR & 0xf):
1003-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_EXTERNAL_INTR, 0);
1004-
break;
1005-
default:
1006-
break;
1007-
}
1008-
}
1009-
#endif /* RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER) */
1010+
rv_check_interrupt(rv);
1011+
#endif
10101012

10111013
if (prev && prev->pc_start != last_pc) {
10121014
/* update previous block */
@@ -1111,6 +1113,43 @@ void rv_step(void *arg)
11111113
#endif
11121114
}
11131115

1116+
void rv_step_debug(void *arg)
1117+
{
1118+
assert(arg);
1119+
riscv_t *rv = arg;
1120+
1121+
#if RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER)
1122+
rv_check_interrupt(rv);
1123+
#endif
1124+
1125+
retranslate:
1126+
/* fetch the next instruction */
1127+
rv_insn_t ir;
1128+
memset(&ir, 0, sizeof(rv_insn_t));
1129+
1130+
uint32_t insn = rv->io.mem_ifetch(rv, rv->PC);
1131+
#if RV32_HAS(SYSTEM)
1132+
if (!insn && need_retranslate) {
1133+
need_retranslate = false;
1134+
goto retranslate;
1135+
}
1136+
#endif
1137+
assert(insn);
1138+
1139+
/* decode the instruction */
1140+
if (!rv_decode(&ir, insn)) {
1141+
rv->compressed = is_compressed(insn);
1142+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, ILLEGAL_INSN, insn);
1143+
return;
1144+
}
1145+
1146+
ir.impl = dispatch_table[ir.opcode];
1147+
ir.pc = rv->PC;
1148+
ir.next = NULL;
1149+
ir.impl(rv, &ir, rv->csr_cycle, rv->PC);
1150+
return;
1151+
}
1152+
11141153
#if RV32_HAS(SYSTEM)
11151154
static void __trap_handler(riscv_t *rv)
11161155
{

‎src/gdbstub.c‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -80,14 +80,12 @@ static gdb_action_t rv_cont(void *args)
8080
{
8181
riscv_t *rv = (riscv_t *) args;
8282
assert(rv);
83-
vm_attr_t *attr = PRIV(rv);
84-
attr->cycle_per_step = 1;
8583

8684
for (; !rv_has_halted(rv) && !rv_is_interrupt(rv);) {
8785
if (breakpoint_map_find(rv->breakpoint_map, rv_get_pc(rv)))
8886
break;
8987

90-
rv_step(rv);
88+
rv_step_debug(rv);
9189
}
9290

9391
/* Clear the interrupt if it's pending */
@@ -100,10 +98,8 @@ static gdb_action_t rv_stepi(void *args)
10098
{
10199
riscv_t *rv = (riscv_t *) args;
102100
assert(rv);
103-
vm_attr_t *attr = PRIV(rv);
104-
attr->cycle_per_step = 1;
105101

106-
rv_step(rv);
102+
rv_step_debug(rv);
107103
return ACT_RESUME;
108104
}
109105

‎src/riscv.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -454,6 +454,9 @@ void rv_debug(riscv_t *rv);
454454
/* step the RISC-V emulator */
455455
void rv_step(void *arg);
456456

457+
/* step the RISC-V emulator for debug mode */
458+
void rv_step_debug(void *arg);
459+
457460
/* set the program counter of a RISC-V emulator */
458461
bool rv_set_pc(riscv_t *rv, riscv_word_t pc);
459462

‎src/rv32_template.c‎

Lines changed: 46 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -224,53 +224,61 @@ RVOP(
224224
* In addition, before relocate_enable_mmu, the block maybe retranslated, \
225225
* thus the branch history lookup table should not be updated too. \
226226
*/ \
227-
IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), )) \
227+
IIF(RV32_HAS(GDBSTUB)(if (!rv->debug_mode), )) \
228228
{ \
229-
for (int i = 0; i < HISTORY_SIZE; i++) { \
230-
if (ir->branch_table->PC[i] == PC) { \
231-
MUST_TAIL return ir->branch_table->target[i]->impl( \
232-
rv, ir->branch_table->target[i], cycle, PC); \
229+
IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), )) \
230+
{ \
231+
for (int i = 0; i < HISTORY_SIZE; i++) { \
232+
if (ir->branch_table->PC[i] == PC) { \
233+
MUST_TAIL return ir->branch_table->target[i]->impl( \
234+
rv, ir->branch_table->target[i], cycle, PC); \
235+
} \
236+
} \
237+
block_t *block = block_find(&rv->block_map, PC); \
238+
if (block) { \
239+
/* update branch history table */ \
240+
ir->branch_table->PC[ir->branch_table->idx] = PC; \
241+
ir->branch_table->target[ir->branch_table->idx] = \
242+
block->ir_head; \
243+
ir->branch_table->idx = \
244+
(ir->branch_table->idx + 1) % HISTORY_SIZE; \
245+
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, \
246+
cycle, PC); \
233247
} \
234248
} \
235-
block_t *block = block_find(&rv->block_map, PC); \
249+
}
250+
#else
251+
#define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE() \
252+
IIF(RV32_HAS(GDBSTUB)(if (!rv->debug_mode), )) \
253+
{ \
254+
block_t *block = cache_get(rv->block_cache, PC, true); \
236255
if (block) { \
256+
for (int i = 0; i < HISTORY_SIZE; i++) { \
257+
if (ir->branch_table->PC[i] == PC) { \
258+
ir->branch_table->times[i]++; \
259+
if (cache_hot(rv->block_cache, PC)) \
260+
goto end_op; \
261+
} \
262+
} \
237263
/* update branch history table */ \
238-
ir->branch_table->PC[ir->branch_table->idx] = PC; \
239-
ir->branch_table->target[ir->branch_table->idx] = block->ir_head; \
240-
ir->branch_table->idx = \
241-
(ir->branch_table->idx + 1) % HISTORY_SIZE; \
264+
int min_idx = 0; \
265+
for (int i = 0; i < HISTORY_SIZE; i++) { \
266+
if (!ir->branch_table->times[i]) { \
267+
min_idx = i; \
268+
break; \
269+
} else if (ir->branch_table->times[min_idx] > \
270+
ir->branch_table->times[i]) { \
271+
min_idx = i; \
272+
} \
273+
} \
274+
ir->branch_table->times[min_idx] = ir->branch_table->PC[min_idx] = \
275+
PC; \
276+
if (cache_hot(rv->block_cache, PC)) \
277+
goto end_op; \
242278
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, \
243279
PC); \
244280
} \
245281
}
246-
#else
247-
#define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE() \
248-
block_t *block = cache_get(rv->block_cache, PC, true); \
249-
if (block) { \
250-
for (int i = 0; i < HISTORY_SIZE; i++) { \
251-
if (ir->branch_table->PC[i] == PC) { \
252-
ir->branch_table->times[i]++; \
253-
if (cache_hot(rv->block_cache, PC)) \
254-
goto end_op; \
255-
} \
256-
} \
257-
/* update branch history table */ \
258-
int min_idx = 0; \
259-
for (int i = 0; i < HISTORY_SIZE; i++) { \
260-
if (!ir->branch_table->times[i]) { \
261-
min_idx = i; \
262-
break; \
263-
} else if (ir->branch_table->times[min_idx] > \
264-
ir->branch_table->times[i]) { \
265-
min_idx = i; \
266-
} \
267-
} \
268-
ir->branch_table->times[min_idx] = 1; \
269-
ir->branch_table->PC[min_idx] = PC; \
270-
if (cache_hot(rv->block_cache, PC)) \
271-
goto end_op; \
272-
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, PC); \
273-
}
274282
#endif
275283

276284
/* The indirect jump instruction JALR uses the I-type encoding. The target

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