Merge pull request #11 from xiaohan484/master

Support RISC-V Compressed Instructions

Author: jserv

Makefile

@@ -16,6 +16,7 @@ CFLAGS += -D ENABLE_Zicsr
 CFLAGS += -D ENABLE_Zifencei
 CFLAGS += -D ENABLE_RV32A
 CFLAGS += -D DEFAULT_STACK_ADDR=0xFFFFF000
+CFLAGS += -D ENABLE_RV32C
 
 # Experimental SDL oriented system calls
 CFLAGS += -D ENABLE_SDL

README.md

@@ -1,4 +1,4 @@
-# RISC-V RV32I[MA] emulator with ELF support
+# RISC-V RV32I[MAC] emulator with ELF support
 
 `rv32emu` is an instruction set architecture (ISA) emulator implementing the 32 bit RISC-V processor model.
 
@@ -35,6 +35,7 @@ should appear when Doom is loaded and executed.
 `rv32emu` is configurable, and you can modify `Makefile` to fit your expectations:
 * `ENABLE_RV32M`: Standard Extension for Integer Multiplication and Division
 * `ENABLE_RV32A`: Standard Extension for Atomic Instructions
+* `ENABLE_RV32C`: Standard Extension for Compressed Instructions (RV32C.F excluded)
 * `Zicsr`: Control and Status Register (CSR)
 * `Zifencei`: Instruction-Fetch Fence
 

io.c

@@ -70,7 +70,7 @@ uint32_t memory_read_str(memory_t *m, uint8_t *dst, uint32_t addr, uint32_t max)
 uint32_t memory_read_ifetch(memory_t *m, uint32_t addr)
 {
     const uint32_t addr_lo = addr & mask_lo;
-    assert((addr_lo & 3) == 0);
+    assert((addr_lo & 1) == 0);
 
     chunk_t *c = m->chunks[addr >> 16];
     assert(c);