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Refactor exception handler
1 parent c39da6f commit 55f30c9

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1 file changed

+31
-25
lines changed

1 file changed

+31
-25
lines changed

‎src/emulate.c‎

Lines changed: 31 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@ static void rv_exception_default_handler(riscv_t *rv)
5555
}
5656

5757
#define EXCEPTION_HANDLER_IMPL(type, code) \
58-
static void rv_except_##type(riscv_t *rv, uint32_t mtval) \
58+
static void rv_except_##type(riscv_t *rv, uint32_t mtval, \
59+
uint8_t insn_len) \
5960
{ \
6061
/* mtvec (Machine Trap-Vector Base Address Register) \
6162
* mtvec[MXLEN-1:2]: vector base address \
@@ -71,6 +72,7 @@ static void rv_exception_default_handler(riscv_t *rv)
7172
rv->csr_mtval = mtval; \
7273
rv->csr_mcause = code; \
7374
if (!rv->csr_mtvec) { /* in case CSR is not configured */ \
75+
rv->compressed = (insn_len == INSN_16); \
7476
rv_exception_default_handler(rv); \
7577
return; \
7678
} \
@@ -254,10 +256,14 @@ static bool insn_is_misaligned(uint32_t pc)
254256
);
255257
}
256258

259+
#define RV_Op(OPCODE) static bool op_##OPCODE(riscv_t *rv, rv_insn_t *ir)
260+
#define EMU_Op(OPCODE, RV, IR) op_##OPCODE(RV, IR)
261+
262+
257263
static bool emulate(riscv_t *rv, rv_insn_t *ir)
258264
{
259265
/* check instruction is compressed or not */
260-
rv->compressed = (ir->insn_len == INSN_16);
266+
// rv->compressed = (ir->insn_len == INSN_16);
261267

262268
switch (ir->opcode) {
263269
/* RV32I Base Instruction Set */
@@ -290,7 +296,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
290296
rv->X[ir->rd] = pc + ir->insn_len;
291297
/* check instruction misaligned */
292298
if (insn_is_misaligned(rv->PC)) {
293-
rv_except_insn_misaligned(rv, pc);
299+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
294300
return false;
295301
}
296302
/* can branch */
@@ -312,7 +318,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
312318
rv->X[ir->rd] = pc + ir->insn_len;
313319
/* check instruction misaligned */
314320
if (insn_is_misaligned(rv->PC)) {
315-
rv_except_insn_misaligned(rv, pc);
321+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
316322
return false;
317323
}
318324
/* can branch */
@@ -324,7 +330,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
324330
rv->PC += ir->imm;
325331
/* check instruction misaligned */
326332
if (insn_is_misaligned(rv->PC)) {
327-
rv_except_insn_misaligned(rv, pc);
333+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
328334
return false;
329335
}
330336
/* can branch */
@@ -338,7 +344,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
338344
rv->PC += ir->imm;
339345
/* check instruction misaligned */
340346
if (insn_is_misaligned(rv->PC)) {
341-
rv_except_insn_misaligned(rv, pc);
347+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
342348
return false;
343349
}
344350
/* can branch */
@@ -352,7 +358,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
352358
rv->PC += ir->imm;
353359
/* check instruction misaligned */
354360
if (insn_is_misaligned(rv->PC)) {
355-
rv_except_insn_misaligned(rv, pc);
361+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
356362
return false;
357363
}
358364
/* can branch */
@@ -366,7 +372,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
366372
rv->PC += ir->imm;
367373
/* check instruction misaligned */
368374
if (insn_is_misaligned(rv->PC)) {
369-
rv_except_insn_misaligned(rv, pc);
375+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
370376
return false;
371377
}
372378
/* can branch */
@@ -380,7 +386,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
380386
rv->PC += ir->imm;
381387
/* check instruction misaligned */
382388
if (insn_is_misaligned(rv->PC)) {
383-
rv_except_insn_misaligned(rv, pc);
389+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
384390
return false;
385391
}
386392
/* can branch */
@@ -394,7 +400,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
394400
rv->PC += ir->imm;
395401
/* check instruction misaligned */
396402
if (insn_is_misaligned(rv->PC)) {
397-
rv_except_insn_misaligned(rv, pc);
403+
rv_except_insn_misaligned(rv, pc, ir->insn_len);
398404
return false;
399405
}
400406
/* can branch */
@@ -409,7 +415,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
409415
case rv_insn_lh: { /* LH: Load Halfword */
410416
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
411417
if (addr & 1) {
412-
rv_except_load_misaligned(rv, addr);
418+
rv_except_load_misaligned(rv, addr, ir->insn_len);
413419
return false;
414420
}
415421
rv->X[ir->rd] = sign_extend_h(rv->io.mem_read_s(rv, addr));
@@ -418,7 +424,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
418424
case rv_insn_lw: { /* LW: Load Word */
419425
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
420426
if (addr & 3) {
421-
rv_except_load_misaligned(rv, addr);
427+
rv_except_load_misaligned(rv, addr, ir->insn_len);
422428
return false;
423429
}
424430
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
@@ -430,7 +436,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
430436
case rv_insn_lhu: { /* LHU: Load Halfword Unsigned */
431437
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
432438
if (addr & 1) {
433-
rv_except_load_misaligned(rv, addr);
439+
rv_except_load_misaligned(rv, addr, ir->insn_len);
434440
return false;
435441
}
436442
rv->X[ir->rd] = rv->io.mem_read_s(rv, addr);
@@ -442,7 +448,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
442448
case rv_insn_sh: { /* SH: Store Halfword */
443449
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
444450
if (addr & 1) {
445-
rv_except_store_misaligned(rv, addr);
451+
rv_except_store_misaligned(rv, addr, ir->insn_len);
446452
return false;
447453
}
448454
rv->io.mem_write_s(rv, addr, rv->X[ir->rs2]);
@@ -451,7 +457,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
451457
case rv_insn_sw: { /* SW: Store Word */
452458
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
453459
if (addr & 3) {
454-
rv_except_store_misaligned(rv, addr);
460+
rv_except_store_misaligned(rv, addr, ir->insn_len);
455461
return false;
456462
}
457463
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
@@ -931,7 +937,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
931937
*/
932938
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
933939
if (addr & 3) {
934-
rv_except_load_misaligned(rv, addr);
940+
rv_except_load_misaligned(rv, addr, ir->insn_len);
935941
return false;
936942
}
937943
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
@@ -945,7 +951,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
945951
*/
946952
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
947953
if (addr & 3) {
948-
rv_except_store_misaligned(rv, addr);
954+
rv_except_store_misaligned(rv, addr, ir->insn_len);
949955
return false;
950956
}
951957
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
@@ -967,7 +973,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
967973
rv->X[1] = rv->PC + ir->insn_len;
968974
rv->PC += ir->imm;
969975
if (rv->PC & 0x1) {
970-
rv_except_insn_misaligned(rv, rv->PC);
976+
rv_except_insn_misaligned(rv, rv->PC, ir->insn_len);
971977
return false;
972978
}
973979
/* can branch */
@@ -1044,7 +1050,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10441050
*/
10451051
rv->PC += ir->imm;
10461052
if (rv->PC & 0x1) {
1047-
rv_except_insn_misaligned(rv, rv->PC);
1053+
rv_except_insn_misaligned(rv, rv->PC, ir->insn_len);
10481054
return false;
10491055
}
10501056
/* can branch */
@@ -1074,7 +1080,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10741080
case rv_insn_clwsp: { /* C.LWSP */
10751081
const uint32_t addr = rv->X[rv_reg_sp] + ir->imm;
10761082
if (addr & 3) {
1077-
rv_except_load_misaligned(rv, addr);
1083+
rv_except_load_misaligned(rv, addr, ir->insn_len);
10781084
return false;
10791085
}
10801086
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
@@ -1097,7 +1103,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10971103
rv->X[rv_reg_ra] = rv->PC + ir->insn_len;
10981104
rv->PC = jump_to;
10991105
if (rv->PC & 0x1) {
1100-
rv_except_insn_misaligned(rv, rv->PC);
1106+
rv_except_insn_misaligned(rv, rv->PC, ir->insn_len);
11011107
return false;
11021108
}
11031109
/* can branch */
@@ -1116,7 +1122,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
11161122
case rv_insn_cswsp: { /* C.SWSP */
11171123
const uint32_t addr = rv->X[2] + ir->imm;
11181124
if (addr & 3) {
1119-
rv_except_store_misaligned(rv, addr);
1125+
rv_except_store_misaligned(rv, addr, ir->insn_len);
11201126
return false;
11211127
}
11221128
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
@@ -1252,7 +1258,7 @@ static void block_translate(riscv_t *rv, block_t *block)
12521258

12531259
/* decode the instruction */
12541260
if (!rv_decode(ir, insn)) {
1255-
rv_except_illegal_insn(rv, insn);
1261+
rv_except_illegal_insn(rv, insn, ir->insn_len);
12561262
break;
12571263
}
12581264

@@ -1336,12 +1342,12 @@ void rv_step(riscv_t *rv, int32_t cycles)
13361342
void ebreak_handler(riscv_t *rv)
13371343
{
13381344
assert(rv);
1339-
rv_except_breakpoint(rv, rv->PC);
1345+
rv_except_breakpoint(rv, rv->PC, 0);
13401346
}
13411347

13421348
void ecall_handler(riscv_t *rv)
13431349
{
13441350
assert(rv);
1345-
rv_except_ecall_M(rv, 0);
1351+
rv_except_ecall_M(rv, 0, 0);
13461352
syscall_handler(rv);
13471353
}

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