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Kai Luo
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[DAGCombiner] Enhance (zext(setcc))
Current `v:t = zext(setcc x,y,cc)` will be transformed to `select x, y, 1:t, 0:t, cc`. It misses some opportunities if x's type size is less than `t`'s size. This patch enhances the above transformation. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D86687
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6 files changed

+56
-73
lines changed

6 files changed

+56
-73
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10536,13 +10536,16 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1053610536
N0.getValueType());
1053710537
}
1053810538

10539-
// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
10539+
// zext(setcc x,y,cc) -> zext(select x, y, true, false, cc)
1054010540
SDLoc DL(N);
10541+
EVT N0VT = N0.getValueType();
10542+
EVT N00VT = N0.getOperand(0).getValueType();
1054110543
if (SDValue SCC = SimplifySelectCC(
10542-
DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
10543-
DAG.getConstant(0, DL, VT),
10544+
DL, N0.getOperand(0), N0.getOperand(1),
10545+
DAG.getBoolConstant(true, DL, N0VT, N00VT),
10546+
DAG.getBoolConstant(false, DL, N0VT, N00VT),
1054410547
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
10545-
return SCC;
10548+
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC);
1054610549
}
1054710550

1054810551
// (zext (shl (zext x), cst)) -> (shl (zext x), cst)

‎llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -310,18 +310,10 @@ define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
310310
ret i1 %res
311311
}
312312

313-
;------------------------------------------------------------------------------;
314-
; A few negative tests
315-
;------------------------------------------------------------------------------;
316-
317-
define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
318-
; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
313+
define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
314+
; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
319315
; CHECK: // %bb.0:
320-
; CHECK-NEXT: mov w8, #24
321-
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
322-
; CHECK-NEXT: lsr w8, w8, w1
323-
; CHECK-NEXT: tst w8, w0
324-
; CHECK-NEXT: cset w0, lt
316+
; CHECK-NEXT: mov w0, wzr
325317
; CHECK-NEXT: ret
326318
%t0 = lshr i8 24, %y
327319
%t1 = and i8 %t0, %x

‎llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -316,20 +316,14 @@ define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
316316
ret i1 %res
317317
}
318318

319-
;------------------------------------------------------------------------------;
320-
; A few negative tests
321-
;------------------------------------------------------------------------------;
322-
323-
define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
324-
; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
319+
define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
320+
; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
325321
; CHECK: // %bb.0:
326322
; CHECK-NEXT: mov w8, #24
327323
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
328324
; CHECK-NEXT: lsl w8, w8, w1
329325
; CHECK-NEXT: and w8, w8, w0
330-
; CHECK-NEXT: sxtb w8, w8
331-
; CHECK-NEXT: cmp w8, #0 // =0
332-
; CHECK-NEXT: cset w0, lt
326+
; CHECK-NEXT: ubfx w0, w8, #7, #1
333327
; CHECK-NEXT: ret
334328
%t0 = shl i8 24, %y
335329
%t1 = and i8 %t0, %x

‎llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1489,7 +1489,7 @@ define i32 @fcmp_olt_f128(fp128 %a, fp128 %b) #0 {
14891489
; P8-NEXT: stdu r1, -112(r1)
14901490
; P8-NEXT: bl __ltkf2
14911491
; P8-NEXT: nop
1492-
; P8-NEXT: srwi r3, r3, 31
1492+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
14931493
; P8-NEXT: addi r1, r1, 112
14941494
; P8-NEXT: ld r0, 16(r1)
14951495
; P8-NEXT: mtlr r0
@@ -1510,7 +1510,7 @@ define i32 @fcmp_olt_f128(fp128 %a, fp128 %b) #0 {
15101510
; NOVSX-NEXT: stdu r1, -32(r1)
15111511
; NOVSX-NEXT: bl __ltkf2
15121512
; NOVSX-NEXT: nop
1513-
; NOVSX-NEXT: srwi r3, r3, 31
1513+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
15141514
; NOVSX-NEXT: addi r1, r1, 32
15151515
; NOVSX-NEXT: ld r0, 16(r1)
15161516
; NOVSX-NEXT: mtlr r0
@@ -1619,8 +1619,8 @@ define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 {
16191619
; P8-NEXT: stdu r1, -112(r1)
16201620
; P8-NEXT: bl __gekf2
16211621
; P8-NEXT: nop
1622-
; P8-NEXT: not r3, r3
1623-
; P8-NEXT: srwi r3, r3, 31
1622+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
1623+
; P8-NEXT: xori r3, r3, 1
16241624
; P8-NEXT: addi r1, r1, 112
16251625
; P8-NEXT: ld r0, 16(r1)
16261626
; P8-NEXT: mtlr r0
@@ -1644,8 +1644,8 @@ define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 {
16441644
; NOVSX-NEXT: stdu r1, -32(r1)
16451645
; NOVSX-NEXT: bl __gekf2
16461646
; NOVSX-NEXT: nop
1647-
; NOVSX-NEXT: not r3, r3
1648-
; NOVSX-NEXT: srwi r3, r3, 31
1647+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
1648+
; NOVSX-NEXT: xori r3, r3, 1
16491649
; NOVSX-NEXT: addi r1, r1, 32
16501650
; NOVSX-NEXT: ld r0, 16(r1)
16511651
; NOVSX-NEXT: mtlr r0
@@ -1796,7 +1796,7 @@ define i32 @fcmp_ult_f128(fp128 %a, fp128 %b) #0 {
17961796
; P8-NEXT: stdu r1, -112(r1)
17971797
; P8-NEXT: bl __gekf2
17981798
; P8-NEXT: nop
1799-
; P8-NEXT: srwi r3, r3, 31
1799+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
18001800
; P8-NEXT: addi r1, r1, 112
18011801
; P8-NEXT: ld r0, 16(r1)
18021802
; P8-NEXT: mtlr r0
@@ -1817,7 +1817,7 @@ define i32 @fcmp_ult_f128(fp128 %a, fp128 %b) #0 {
18171817
; NOVSX-NEXT: stdu r1, -32(r1)
18181818
; NOVSX-NEXT: bl __gekf2
18191819
; NOVSX-NEXT: nop
1820-
; NOVSX-NEXT: srwi r3, r3, 31
1820+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
18211821
; NOVSX-NEXT: addi r1, r1, 32
18221822
; NOVSX-NEXT: ld r0, 16(r1)
18231823
; NOVSX-NEXT: mtlr r0
@@ -1922,8 +1922,8 @@ define i32 @fcmp_uge_f128(fp128 %a, fp128 %b) #0 {
19221922
; P8-NEXT: stdu r1, -112(r1)
19231923
; P8-NEXT: bl __ltkf2
19241924
; P8-NEXT: nop
1925-
; P8-NEXT: not r3, r3
1926-
; P8-NEXT: srwi r3, r3, 31
1925+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
1926+
; P8-NEXT: xori r3, r3, 1
19271927
; P8-NEXT: addi r1, r1, 112
19281928
; P8-NEXT: ld r0, 16(r1)
19291929
; P8-NEXT: mtlr r0
@@ -1943,8 +1943,8 @@ define i32 @fcmp_uge_f128(fp128 %a, fp128 %b) #0 {
19431943
; NOVSX-NEXT: stdu r1, -32(r1)
19441944
; NOVSX-NEXT: bl __ltkf2
19451945
; NOVSX-NEXT: nop
1946-
; NOVSX-NEXT: not r3, r3
1947-
; NOVSX-NEXT: srwi r3, r3, 31
1946+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
1947+
; NOVSX-NEXT: xori r3, r3, 1
19481948
; NOVSX-NEXT: addi r1, r1, 32
19491949
; NOVSX-NEXT: ld r0, 16(r1)
19501950
; NOVSX-NEXT: mtlr r0
@@ -2093,7 +2093,7 @@ define i32 @fcmps_olt_f128(fp128 %a, fp128 %b) #0 {
20932093
; P8-NEXT: stdu r1, -112(r1)
20942094
; P8-NEXT: bl __ltkf2
20952095
; P8-NEXT: nop
2096-
; P8-NEXT: srwi r3, r3, 31
2096+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
20972097
; P8-NEXT: addi r1, r1, 112
20982098
; P8-NEXT: ld r0, 16(r1)
20992099
; P8-NEXT: mtlr r0
@@ -2114,7 +2114,7 @@ define i32 @fcmps_olt_f128(fp128 %a, fp128 %b) #0 {
21142114
; NOVSX-NEXT: stdu r1, -32(r1)
21152115
; NOVSX-NEXT: bl __ltkf2
21162116
; NOVSX-NEXT: nop
2117-
; NOVSX-NEXT: srwi r3, r3, 31
2117+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
21182118
; NOVSX-NEXT: addi r1, r1, 32
21192119
; NOVSX-NEXT: ld r0, 16(r1)
21202120
; NOVSX-NEXT: mtlr r0
@@ -2223,8 +2223,8 @@ define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 {
22232223
; P8-NEXT: stdu r1, -112(r1)
22242224
; P8-NEXT: bl __gekf2
22252225
; P8-NEXT: nop
2226-
; P8-NEXT: not r3, r3
2227-
; P8-NEXT: srwi r3, r3, 31
2226+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
2227+
; P8-NEXT: xori r3, r3, 1
22282228
; P8-NEXT: addi r1, r1, 112
22292229
; P8-NEXT: ld r0, 16(r1)
22302230
; P8-NEXT: mtlr r0
@@ -2248,8 +2248,8 @@ define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 {
22482248
; NOVSX-NEXT: stdu r1, -32(r1)
22492249
; NOVSX-NEXT: bl __gekf2
22502250
; NOVSX-NEXT: nop
2251-
; NOVSX-NEXT: not r3, r3
2252-
; NOVSX-NEXT: srwi r3, r3, 31
2251+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
2252+
; NOVSX-NEXT: xori r3, r3, 1
22532253
; NOVSX-NEXT: addi r1, r1, 32
22542254
; NOVSX-NEXT: ld r0, 16(r1)
22552255
; NOVSX-NEXT: mtlr r0
@@ -2400,7 +2400,7 @@ define i32 @fcmps_ult_f128(fp128 %a, fp128 %b) #0 {
24002400
; P8-NEXT: stdu r1, -112(r1)
24012401
; P8-NEXT: bl __gekf2
24022402
; P8-NEXT: nop
2403-
; P8-NEXT: srwi r3, r3, 31
2403+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
24042404
; P8-NEXT: addi r1, r1, 112
24052405
; P8-NEXT: ld r0, 16(r1)
24062406
; P8-NEXT: mtlr r0
@@ -2421,7 +2421,7 @@ define i32 @fcmps_ult_f128(fp128 %a, fp128 %b) #0 {
24212421
; NOVSX-NEXT: stdu r1, -32(r1)
24222422
; NOVSX-NEXT: bl __gekf2
24232423
; NOVSX-NEXT: nop
2424-
; NOVSX-NEXT: srwi r3, r3, 31
2424+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
24252425
; NOVSX-NEXT: addi r1, r1, 32
24262426
; NOVSX-NEXT: ld r0, 16(r1)
24272427
; NOVSX-NEXT: mtlr r0
@@ -2526,8 +2526,8 @@ define i32 @fcmps_uge_f128(fp128 %a, fp128 %b) #0 {
25262526
; P8-NEXT: stdu r1, -112(r1)
25272527
; P8-NEXT: bl __ltkf2
25282528
; P8-NEXT: nop
2529-
; P8-NEXT: not r3, r3
2530-
; P8-NEXT: srwi r3, r3, 31
2529+
; P8-NEXT: rlwinm r3, r3, 1, 31, 31
2530+
; P8-NEXT: xori r3, r3, 1
25312531
; P8-NEXT: addi r1, r1, 112
25322532
; P8-NEXT: ld r0, 16(r1)
25332533
; P8-NEXT: mtlr r0
@@ -2547,8 +2547,8 @@ define i32 @fcmps_uge_f128(fp128 %a, fp128 %b) #0 {
25472547
; NOVSX-NEXT: stdu r1, -32(r1)
25482548
; NOVSX-NEXT: bl __ltkf2
25492549
; NOVSX-NEXT: nop
2550-
; NOVSX-NEXT: not r3, r3
2551-
; NOVSX-NEXT: srwi r3, r3, 31
2550+
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
2551+
; NOVSX-NEXT: xori r3, r3, 1
25522552
; NOVSX-NEXT: addi r1, r1, 32
25532553
; NOVSX-NEXT: ld r0, 16(r1)
25542554
; NOVSX-NEXT: mtlr r0

‎llvm/test/CodeGen/PowerPC/setcc-logic.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) {
1818
; CHECK-LABEL: all_sign_bits_clear:
1919
; CHECK: # %bb.0:
2020
; CHECK-NEXT: or 3, 3, 4
21-
; CHECK-NEXT: not 3, 3
22-
; CHECK-NEXT: srwi 3, 3, 31
21+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
22+
; CHECK-NEXT: xori 3, 3, 1
2323
; CHECK-NEXT: blr
2424
%a = icmp sgt i32 %P, -1
2525
%b = icmp sgt i32 %Q, -1
@@ -46,7 +46,7 @@ define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) {
4646
; CHECK-LABEL: all_sign_bits_set:
4747
; CHECK: # %bb.0:
4848
; CHECK-NEXT: and 3, 3, 4
49-
; CHECK-NEXT: srwi 3, 3, 31
49+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
5050
; CHECK-NEXT: blr
5151
%a = icmp slt i32 %P, 0
5252
%b = icmp slt i32 %Q, 0
@@ -72,7 +72,7 @@ define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) {
7272
; CHECK-LABEL: any_sign_bits_set:
7373
; CHECK: # %bb.0:
7474
; CHECK-NEXT: or 3, 3, 4
75-
; CHECK-NEXT: srwi 3, 3, 31
75+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
7676
; CHECK-NEXT: blr
7777
%a = icmp slt i32 %P, 0
7878
%b = icmp slt i32 %Q, 0
@@ -100,8 +100,8 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) {
100100
; CHECK-LABEL: any_sign_bits_clear:
101101
; CHECK: # %bb.0:
102102
; CHECK-NEXT: and 3, 3, 4
103-
; CHECK-NEXT: not 3, 3
104-
; CHECK-NEXT: srwi 3, 3, 31
103+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
104+
; CHECK-NEXT: xori 3, 3, 1
105105
; CHECK-NEXT: blr
106106
%a = icmp sgt i32 %P, -1
107107
%b = icmp sgt i32 %Q, -1

‎llvm/test/CodeGen/PowerPC/signbit-shift.ll

Lines changed: 13 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
define i32 @zext_ifpos(i32 %x) {
77
; CHECK-LABEL: zext_ifpos:
88
; CHECK: # %bb.0:
9-
; CHECK-NEXT: not 3, 3
10-
; CHECK-NEXT: srwi 3, 3, 31
9+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
10+
; CHECK-NEXT: xori 3, 3, 1
1111
; CHECK-NEXT: blr
1212
%c = icmp sgt i32 %x, -1
1313
%e = zext i1 %c to i32
@@ -45,10 +45,9 @@ define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
4545
define i32 @sel_ifpos_tval_bigger(i32 %x) {
4646
; CHECK-LABEL: sel_ifpos_tval_bigger:
4747
; CHECK: # %bb.0:
48-
; CHECK-NEXT: li 4, 41
49-
; CHECK-NEXT: cmpwi 3, -1
50-
; CHECK-NEXT: li 3, 42
51-
; CHECK-NEXT: iselgt 3, 3, 4
48+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
49+
; CHECK-NEXT: xori 3, 3, 1
50+
; CHECK-NEXT: addi 3, 3, 41
5251
; CHECK-NEXT: blr
5352
%c = icmp sgt i32 %x, -1
5453
%r = select i1 %c, i32 42, i32 41
@@ -97,10 +96,9 @@ define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
9796
define i32 @sel_ifpos_fval_bigger(i32 %x) {
9897
; CHECK-LABEL: sel_ifpos_fval_bigger:
9998
; CHECK: # %bb.0:
100-
; CHECK-NEXT: li 4, 42
101-
; CHECK-NEXT: cmpwi 3, -1
102-
; CHECK-NEXT: li 3, 41
103-
; CHECK-NEXT: iselgt 3, 3, 4
99+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
100+
; CHECK-NEXT: xori 3, 3, 1
101+
; CHECK-NEXT: subfic 3, 3, 42
104102
; CHECK-NEXT: blr
105103
%c = icmp sgt i32 %x, -1
106104
%r = select i1 %c, i32 41, i32 42
@@ -112,7 +110,7 @@ define i32 @sel_ifpos_fval_bigger(i32 %x) {
112110
define i32 @zext_ifneg(i32 %x) {
113111
; CHECK-LABEL: zext_ifneg:
114112
; CHECK: # %bb.0:
115-
; CHECK-NEXT: srwi 3, 3, 31
113+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
116114
; CHECK-NEXT: blr
117115
%c = icmp slt i32 %x, 0
118116
%r = zext i1 %c to i32
@@ -134,10 +132,8 @@ define i32 @add_zext_ifneg(i32 %x) {
134132
define i32 @sel_ifneg_tval_bigger(i32 %x) {
135133
; CHECK-LABEL: sel_ifneg_tval_bigger:
136134
; CHECK: # %bb.0:
137-
; CHECK-NEXT: li 4, 41
138-
; CHECK-NEXT: cmpwi 3, 0
139-
; CHECK-NEXT: li 3, 42
140-
; CHECK-NEXT: isellt 3, 3, 4
135+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
136+
; CHECK-NEXT: addi 3, 3, 41
141137
; CHECK-NEXT: blr
142138
%c = icmp slt i32 %x, 0
143139
%r = select i1 %c, i32 42, i32 41
@@ -169,10 +165,8 @@ define i32 @add_sext_ifneg(i32 %x) {
169165
define i32 @sel_ifneg_fval_bigger(i32 %x) {
170166
; CHECK-LABEL: sel_ifneg_fval_bigger:
171167
; CHECK: # %bb.0:
172-
; CHECK-NEXT: li 4, 42
173-
; CHECK-NEXT: cmpwi 3, 0
174-
; CHECK-NEXT: li 3, 41
175-
; CHECK-NEXT: isellt 3, 3, 4
168+
; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
169+
; CHECK-NEXT: subfic 3, 3, 42
176170
; CHECK-NEXT: blr
177171
%c = icmp slt i32 %x, 0
178172
%r = select i1 %c, i32 41, i32 42

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