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Merge pull request #1291 from fpistm/WB_fix
WB enhancements
2 parents a12e123 + 89e2f09 commit 82cdead

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-445
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18 files changed

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‎cores/arduino/board.h‎

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@@ -12,6 +12,7 @@
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#include "digital_io.h"
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#include "dwt.h"
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#include "hw_config.h"
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#include "otp.h"
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#include "timer.h"
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#include "uart.h"
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‎cores/arduino/stm32/clock.h‎

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@@ -1,39 +1,15 @@
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/**
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******************************************************************************
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* @file clock.h
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* @author WI6LABS
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* @version V1.0.0
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* @date 01-August-2016
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* @brief Header for clock.c module
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/*
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*******************************************************************************
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* Copyright (c) 2016-2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __CLOCK_H
@@ -62,6 +38,8 @@ uint32_t getCurrentMillis(void);
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uint32_t getCurrentMicros(void);
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void enableClock(sourceClock_t source);
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void configHSECapacitorTuning(void);
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#ifdef __cplusplus
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}
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#endif

‎cores/arduino/stm32/lock_resource.h‎

Lines changed: 168 additions & 25 deletions
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@@ -1,27 +1,22 @@
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/**
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******************************************************************************
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* @file lock_resource.h
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* @author MCD Application Team
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* @brief Header for lock_resource.c
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/*
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*******************************************************************************
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* Copyright (c) 2019-2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _LOCK_RESOURCE_H
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#define _LOCK_RESOURCE_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32_def.h"
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#include "stm32yyxx_ll_hsem.h"
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#ifdef __cplusplus
2722
extern "C" {
@@ -35,15 +30,163 @@ typedef enum {
3530
} LockResource_Status_t;
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3732
/* Exported constants --------------------------------------------------------*/
38-
#define LOCK_RESOURCE_TIMEOUT 100U /* timeout in ms */
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#if defined(STM32WBxx)
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/*
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* HW semaphore Complement ID list defined in hw_conf.h from STM32WB.
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* They could be used also for H7 dualcore targets.
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*/
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/*
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* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or
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* erase data in flash. The CPU1 shall not either write or erase in flash when
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* this semaphore is taken by the CPU2. When the CPU1 needs to either write or
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* erase in flash, it shall first get the semaphore and release it just
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* after writing a raw (64bits data) or erasing one sector.
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* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and
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* CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its
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* timing. The CPU1 may request the CPU2 to use the semaphore instead of the
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* PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
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*/
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7U
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40-
/* Exported macro ------------------------------------------------------------*/
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#define PERIPH_LOCK(__Periph__) Periph_Lock(__Periph__, LOCK_RESOURCE_TIMEOUT)
42-
#define PERIPH_UNLOCK(__Periph__) Periph_Unlock(__Periph__)
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/*
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* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or
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* erase data in flash. In order to protect its timing, the CPU1 may get this
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* semaphore to prevent the CPU2 to either write or erase in flash
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* (as this will stall both CPUs)
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* The PES bit shall not be used as this may stall the CPU2 in some cases.
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*/
58+
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6U
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44-
/* Exported functions ------------------------------------------------------- */
45-
LockResource_Status_t Periph_Lock(void *Peripheral, uint32_t Timeout);
46-
void Periph_Unlock(void *Peripheral);
60+
/*
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* Index of the semaphore used to manage the CLK48 clock configuration
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* When the USB is required, this semaphore shall be taken before configuring
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* the CLK48 for USB and should be released after the application switch OFF
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* the clock when the USB is not used anymore. When using the RNG, it is good
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* enough to use CFG_HW_RNG_SEMID to control CLK48.
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* More details in AN5289
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*/
68+
#define CFG_HW_CLK48_CONFIG_SEMID 5U
69+
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID CFG_HW_CLK48_CONFIG_SEMID
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/* Index of the semaphore used to manage the entry Stop Mode procedure */
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#define CFG_HW_ENTRY_STOP_MODE_SEMID 4U
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#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1U << CFG_HW_ENTRY_STOP_MODE_SEMID)
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/* Index of the semaphore used to access the RCC */
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#define CFG_HW_RCC_SEMID 3U
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/* Index of the semaphore used to access the FLASH */
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#define CFG_HW_FLASH_SEMID 2U
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/* Index of the semaphore used to access the PKA */
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#define CFG_HW_PKA_SEMID 1U
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/* Index of the semaphore used to access the RNG */
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#define CFG_HW_RNG_SEMID 0U
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/* Index of the semaphore used to access GPIO */
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#define CFG_HW_GPIO_SEMID 8U
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90+
/* Index of the semaphore used to access the EXTI */
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#define CFG_HW_EXTI_SEMID 9U
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93+
#elif defined(STM32MP1xx)
94+
/*
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* HW semaphore from STM32MP1
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* EXTI and GPIO are inherited from STM32MP1 Linux.
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* Other SEMID are not used by linux and must not be used here,
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* but reserved for MPU.
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*/
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/* Index of the semaphore used to access GPIO */
101+
#define CFG_HW_GPIO_SEMID 0U
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/* Index of the semaphore used to access the EXTI */
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#define CFG_HW_EXTI_SEMID 1U
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#endif /* STM32WBxx */
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107+
/* Fake semaphore ID definition for compilation purpose only */
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#ifndef HSEM_SEMID_MAX
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#define HSEM_SEMID_MAX 0U
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#endif
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#ifndef CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_CLK48_CONFIG_SEMID
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#define CFG_HW_CLK48_CONFIG_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_RCC_CRRCR_CCIPR_SEMID
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#define CFG_HW_RCC_CRRCR_CCIPR_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_ENTRY_STOP_MODE_SEMID
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#define CFG_HW_ENTRY_STOP_MODE_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_RCC_SEMID
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#define CFG_HW_RCC_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_FLASH_SEMID
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#define CFG_HW_FLASH_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_PKA_SEMID
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#define CFG_HW_PKA_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_RNG_SEMID
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#define CFG_HW_RNG_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_GPIO_SEMID
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#define CFG_HW_GPIO_SEMID (HSEM_SEMID_MAX +1)
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#endif
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#ifndef CFG_HW_EXTI_SEMID
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#define CFG_HW_EXTI_SEMID (HSEM_SEMID_MAX +1)
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#endif
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/* Hardware Semaphore wait forever value */
146+
#define HSEM_LOCK_WAIT_FOREVER 0xFFFFFFFFU
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/* Hardware Semaphore default retry value */
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#ifndef HSEM_LOCK_DEFAULT_RETRY
149+
#define HSEM_LOCK_DEFAULT_RETRY 0xFFFFU
150+
#endif
151+
152+
/*
153+
* @brief hsem_lock function is used for register protection of shared Peripheral
154+
* and shall be called before accessing registers of this shared Peripheral
155+
* If Semaphore id is already taken, the function will busy loop waiting for it to
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* be released, but give up after @retry downcounter have elapsed
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* @param semID: Semaphore id used to identify which peripheral to protect
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* @param retry: number of retry
159+
* @retval None
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*/
161+
static inline void hsem_lock(uint32_t semID, uint32_t retry)
162+
{
163+
#if defined(STM32MP1xx) || defined(STM32WBxx)
164+
if ((semID) <= HSEM_SEMID_MAX) {
165+
while (LL_HSEM_1StepLock(HSEM, semID)) {
166+
if (retry != HSEM_LOCK_WAIT_FOREVER) {
167+
retry--;
168+
if (retry == 0) {
169+
Error_Handler();
170+
}
171+
}
172+
}
173+
}
174+
#endif /* STM32MP1xx || STM32WBxx */
175+
}
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/*
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* @brief hsem_unlock released a previously-acquired semaphore
179+
* @param semID Semaphore id used to identify which peripheral to release
180+
* @retval None
181+
*/
182+
static inline void hsem_unlock(uint32_t semID)
183+
{
184+
#if defined(STM32MP1xx) || defined(STM32WBxx)
185+
if ((semID) <= HSEM_SEMID_MAX) {
186+
LL_HSEM_ReleaseLock(HSEM, semID, 0);
187+
}
188+
#endif /* STM32MP1xx || STM32WBxx */
189+
}
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48191
#ifdef __cplusplus
49192
} // extern "C"

‎cores/arduino/stm32/otp.h‎

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1+
/*
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*******************************************************************************
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* Copyright (c) 2021, STMicroelectronics
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* All rights reserved.
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*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
14+
/* Define to prevent recursive inclusion -------------------------------------*/
15+
#ifndef __OTP_H
16+
#define __OTP_H
17+
18+
#include "stm32_def.h"
19+
20+
#ifdef OTP_AREA_BASE
21+
#ifdef __cplusplus
22+
extern "C" {
23+
#endif
24+
25+
#ifdef STM32WBxx
26+
/*
27+
* See AN5042: Precise HSE frequency and startup time tuning
28+
* for STM32 wireless MCUs. Each OTP structure type is indicated
29+
* by its index (one byte).The index used for the BT structure is 0.
30+
*/
31+
typedef struct __packed {
32+
uint8_t bd_address[6];
33+
uint8_t hse_tuning;
34+
uint8_t id;
35+
} OTP_BT_t;
36+
#endif /* STM32WBxx */
37+
38+
/* Exported functions --------------------------------------------------------*/
39+
40+
/**
41+
* @brief This API return the address (64 bits aligned) of the ID parameter in the OTP
42+
* It returns the first ID declaration found from the higher address down to the base address
43+
* The user shall fill the OTP from the base address to the top of the OTP so that the more recent
44+
* declaration is returned by the API
45+
* The OTP manager handles only 64 bits parameter
46+
* | Id | Parameter |
47+
* | 8bits | 58bits |
48+
* | MSB | LSB |
49+
*
50+
* @param id: ID of the parameter to read from OTP
51+
* @retval Address of the ID in the OTP - returns 0 when no ID found
52+
*/
53+
uint8_t *OTP_Read(uint8_t id);
54+
55+
#ifdef __cplusplus
56+
}
57+
#endif
58+
#endif /* OTP_AREA_BASE */
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#endif /*__OTP_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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