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Overhaul of RCC, GPIO, Serial. Add SPI, Delay #2
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Overhaul of RCC, GPIO, Serial. Add SPI, Delay #2
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* Working support for RCC configuration, with example * Working support for SPI, with example * Working support for Serial, with example * Working support for Delay, with example * Add memory.x * Add rustfmt.toml * Added myself as an author The RCC peripheral returns a "Core Clock Distribution and Reset" structure, which represents that the core clock configuration is frozen. However we retain the right to switch most PKSUs on the fly, to fine-tune PLL frequencies, and to enable / reset peripherals. For now, use a local build of the stm32h7 crate. This keeps us up-to-date without Adam having to issue patch releases all the time. Hopefully this will stabilise and can be reverted soon. This is documented in the "hacking" section of the README Tested on STM32H743 Rev Y stm32h7xx-hal PR #2 See PR #1 for context
* Working support for RCC configuration, with example * Working support for SPI, with example * Working support for Serial, with example * Working support for Delay, with example * Add memory.x * Add rustfmt.toml * Added myself as an author The RCC peripheral returns a "Core Clock Distribution and Reset" structure, which represents that the core clock configuration is frozen. However we retain the right to switch most PKSUs on the fly, to fine-tune PLL frequencies, and to enable / reset peripherals. For now, use a local build of the stm32h7 crate. This keeps us up-to-date without Adam having to issue patch releases all the time. Hopefully this will stabilise and can be reverted soon. This is documented in the "hacking" section of the README Tested on STM32H743 Rev Y stm32h7xx-hal PR #2 See PR #1 for context
Wow, this is a lot, thanks for the PR. At first glance, it looks like you've done the hard work of getting quite some things working that I hadn't managed yet, so this is really welcome. It will take me a little while to go over this but I have a question already. Do you think it makes sense to keep the examples in a separate crate? For me, this seems to make sense since probably most examples will depend not just on a h7xx chip, but also on a particular board. I had started the nucleo-h743zi crate for just this. Do you have a nucleo-h743zi? How does this idea sound to you? Thanks again and I will try to test test in the next couple of days. @jordens may also be interested. |
In addition to the above points, which are still open, I now have a few more comments and questions. I was able to get an LED blinking and some bits being toggled using your blinky and spi examples respectively - great! In
It looks like nightly is needed in your PR for the There is quite some ITM logging in the examples. I have never been able to get ITM working when I wasn't connected with a debugger but rather the chip seems to lock up early. Is that the case for you? If so, I think it would be good to put the ITM logging behind a feature gate so that the examples can also be run without a debugger. In
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That sounds great! I'll answer some of your questions
Cargo has first-class support for examples through
A board support crate sounds great! I don't have a nucleo board, and it looks like distributors are out of h743zi boards whilst not yet having the h743zi2 version. When I can I should pick one up.
I couldn't think of an obvious solution to
No, my blinky keeps blinking on external power! There's a useful discussion here perhaps. But debugger misconfigurations and so on are common, so a feature gating the examples would be fine. |
* Working support for RCC configuration, with example * Working support for SPI, with example * Working support for Serial, with example * Working support for Delay, with example * Add memory.x * Add rustfmt.toml * Document codegen options in Cargo.toml * Added myself as an author The RCC peripheral returns a "Core Clock Distribution and Reset" structure, which represents that the core clock configuration is frozen. However we retain the right to switch most PKSUs on the fly, to fine-tune PLL frequencies, and to enable / reset peripherals. For now, use a local build of the stm32h7 crate. This keeps us up-to-date without Adam having to issue patch releases all the time. Hopefully this will stabilise and can be reverted soon. This is documented in the "hacking" section of the README Tested on STM32H743 Rev Y stm32h7xx-hal PR #2 See PR #1 for context
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I'm keeping richardeoin/master up-to-date with this PR, so you can view a rendered README there. |
Looks like
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Impressive.
I'd really like to find some time to see how I can shoehorn my project into using this in practice and figure out whether using the hal would constrain me.
- Since we have quite some documentation on the register field variants now (e.g. RCC and SPI), I think those should be used. It would make several comments redundant.
- I think the IO compensation cell (
syscfg.cccsr
) needs to be configured as well since you seem to cover all frequency ranges supported.
src/rcc.rs
Outdated
let ref1_ck = srcclk / pll1_m; | ||
assert!(ref1_ck >= 1_000_000 && ref1_ck <= 2_000_000); | ||
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// VCO output frequency. Choose the lowest VCO frequency |
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Is this obvious? The higher VCO frequency would give less noise but higher power consumption.
Same for the PFD frequency. Higher is better in terms of noise but worse in terms of power.
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I just picked something here to get it working. I think I agree on the default - it should pick the highest VCO frequency. I dread to think how low the Q of the VCO's planar L is at 150MHz! It already chooses the highest PFD frequency, so that can stay.
Perhaps ultimately we should offer a choice in the config that meets almost all use cases - something like:
pub enum VcoStrategy {
HighPerformance, // VCOH, highest PFD frequency, highest VCO frequency
Normal, // VCOL, highest PFD frequency, highest VCO frequency
LowestPower, // VCOL, lowest PFD frequency, lowest VCO frequency
}
* Working support for RCC configuration, with example * Working support for SPI, with example * Working support for Serial, with example * Working support for Delay, with example * Add memory.x * Add rustfmt.toml * Document codegen options in Cargo.toml * Added myself as an author The RCC peripheral returns a "Core Clock Distribution and Reset" structure, which represents that the core clock configuration is frozen. However we retain the right to switch most PKSUs on the fly, to fine-tune PLL frequencies, and to enable / reset peripherals. For now, use a local build of the stm32h7 crate. This keeps us up-to-date without Adam having to issue patch releases all the time. Hopefully this will stabilise and can be reverted soon. This is documented in the "hacking" section of the README Tested on STM32H743 Rev Y stm32h7xx-hal PR #2 See PR #1 for context
Lower noise, more power consumption. Still using VCOL
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Thanks for the comments @jordens . I'll follow up on your two points over the next few days |
* Assert limits based on voltage scale * Set flash wait states based on voltage scale * Use more register field variants from the PAC * Configure the IO compensation cell in SYSCFG
So crate can be returned to stable once `feature(type_alias_enum_variants)` is stabilised. Document in README
Followed up with the following changes:
Almost ready to merge I think, unless there's further comments. Remaining open points:
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Should we push for a new stm32-rs release now to first land the |
Just adding as a note here from #3 once this PR is merged I'd add my implementations from my stm32h7x3-hal project |
(Sorry for my delay, things have been a bit crazy lately.) Shall I just merge this and we sort out any remaining issues later? I think the crate is only barely useable now and I'm interested in getting everyone onboard as soon as possible. I was thinking about a possible solution to the demo code: rather than putting it in I agree it doesn't make sense to keep this on stable while waiting for @adamgreig @therealprof can you add @jordens @richardeoin and @hargoniX as committers to this repo? I think they are all equally (if not more) qualified than me in this regard. |
Since this is blocking @hargoniX, we should probably go with a merge now. I'm happy to retain the open issues
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Done; if those people want to also join stm32-rs just shout. @astraw, I've also set you as repo admin (as you should have been from the beginning!) so you can manage collaborators (and other admins etc) yourself now. |
@adamgreig I'd love to join the stm32-rs org, I got lots of free time in the next months and was planning to work on projects in embedded rust during that time anyways. |
…elay Overhaul of RCC, GPIO, Serial. Add SPI, Delay
Merge upstream
The RCC peripheral returns a "Core Clock Distribution and Reset"
structure, which represents that the core clock configuration is
frozen. However we retain the right to switch most PKSUs on the fly,
to fine-tune PLL frequencies, and to enable / reset peripherals.
For now, use a local build of the stm32h7 crate. This keeps us
up-to-date without Adam having to issue patch releases all the
time. Hopefully the stm32h7 crate will stabilise and can be reverted
soon. This is documented in the "hacking" section of the README.
Tested on STM32H743 Rev Y
stm32h7xx-hal PR #1