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burrbullburrbull
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rebase
1 parent 5fee260 commit 7a5d0e8

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3 files changed

+53
-45
lines changed

3 files changed

+53
-45
lines changed

‎.vscode/settings.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,6 @@
33
"rust-analyzer.check.targets": "thumbv7em-none-eabihf",
44
"rust-analyzer.cargo.features": [
55
"rtic",
6-
"stm32f411"
6+
"stm32f429"
77
],
88
}

‎src/rcc/enable.rs

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -254,6 +254,17 @@ bus_lpenable!(ADC3 => 10);
254254
#[cfg(feature = "adc3")]
255255
bus_reset!(ADC3 => 8);
256256

257+
#[cfg(all(feature = "sai", not(feature = "stm32f446")))]
258+
bus! {
259+
SAI => (APB2, 22),
260+
}
261+
262+
#[cfg(all(feature = "sai", feature = "stm32f446"))]
263+
bus! {
264+
SAI1 => (APB2, 22),
265+
SAI2 => (APB2, 23),
266+
}
267+
257268
#[cfg(feature = "sdio")]
258269
bus! {
259270
SDIO => (APB2, 11),

‎src/sai.rs

Lines changed: 41 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -17,13 +17,13 @@
1717
//! let rcc = ctx.device.RCC.constrain();
1818
//! let clocks = rcc
1919
//! .cfgr
20-
//! .use_hse(8.mhz())
21-
//! .saia_clk(172.mhz())
22-
//! .saib_clk(172.mhz())
20+
//! .use_hse(8.MHz())
21+
//! .saia_clk(172.MHz())
22+
//! .saib_clk(172.MHz())
2323
//! .freeze();
2424
//! // Test that the SAI clock is suitable for 48000KHz audio.
25-
//! assert!(clocks.saia_clk().unwrap() == 172.mhz().into());
26-
//! assert!(clocks.saib_clk().unwrap() == 172.mhz().into());
25+
//! assert!(clocks.saia_clk().unwrap() == 172.MHz().into());
26+
//! assert!(clocks.saib_clk().unwrap() == 172.MHz().into());
2727
//!
2828
//! let gpioe = ctx.device.GPIOE.split();
2929
//! // SAIB is made synchronous to A.
@@ -36,16 +36,16 @@
3636
//! };
3737
//! let tx = saia.master_tx(
3838
//! (
39-
//! gpioe.pe2.into_alternate_af6(),
40-
//! gpioe.pe4.into_alternate_af6(),
41-
//! gpioe.pe5.into_alternate_af6(),
42-
//! gpioe.pe6.into_alternate_af6(),
39+
//! gpioe.pe2.into_alternate(),
40+
//! gpioe.pe4.into_alternate(),
41+
//! gpioe.pe5.into_alternate(),
42+
//! gpioe.pe6.into_alternate(),
4343
//! ),
4444
//! protocol,
45-
//! 48000.hz(),
45+
//! 48.kHz(),
4646
//! clocks,
4747
//! );
48-
//! let rx = saib.slave_rx(gpioe.pe3.into_alternate_af6(), protocol);
48+
//! let rx = saib.slave_rx(gpioe.pe3.into_alternate(), protocol);
4949
//!
5050
//! let mut duplex = Duplex::new(rx, tx);
5151
//! duplex.start();
@@ -63,11 +63,11 @@
6363
//! let rcc = ctx.device.RCC.constrain();
6464
//! let clocks = rcc
6565
//! .cfgr
66-
//! .use_hse(8.mhz())
67-
//! .saia_clk(172.mhz())
66+
//! .use_hse(8.MHz())
67+
//! .saia_clk(172.MHz())
6868
//! .freeze();
6969
//! // Test that the SAI clock is suitable for 48000KHz audio.
70-
//! assert!(clocks.saia_clk().unwrap() == 172.mhz().into());
70+
//! assert!(clocks.saia_clk().unwrap() == 172.MHz());
7171
//!
7272
//! let gpioe = ctx.device.GPIOE.split();
7373
//! let (saia, _) = ctx.device.SAI.split();
@@ -80,13 +80,13 @@
8080
//! };
8181
//! let mut tx = saia.master_tx(
8282
//! (
83-
//! gpioe.pe2.into_alternate_af6(),
84-
//! gpioe.pe4.into_alternate_af6(),
85-
//! gpioe.pe5.into_alternate_af6(),
86-
//! gpioe.pe6.into_alternate_af6(),
83+
//! gpioe.pe2.into_alternate(),
84+
//! gpioe.pe4.into_alternate(),
85+
//! gpioe.pe5.into_alternate(),
86+
//! gpioe.pe6.into_alternate(),
8787
//! ),
8888
//! protocol,
89-
//! 48000.hz(),
89+
//! 48.kHz(),
9090
//! clocks,
9191
//! );
9292
//! tx.start();
@@ -106,16 +106,13 @@
106106
use core::marker::PhantomData;
107107
use core::ops::Deref;
108108

109-
use crate::gpio::gpiod::PD6;
110-
use crate::gpio::gpioe::{PE2, PE3, PE4, PE5, PE6};
111-
use crate::gpio::gpiof::{PF6, PF7, PF8, PF9};
112-
use crate::gpio::{Alternate, AF6};
109+
use crate::gpio::{self, AF6, NoPin};
113110
use crate::rcc::Clocks;
114-
use crate::stm32::RCC;
111+
use crate::pac::RCC;
115112
#[cfg(not(feature = "stm32f446"))]
116-
use crate::stm32::{sai, SAI};
113+
use crate::pac::{sai, SAI};
117114
#[cfg(feature = "stm32f446")]
118-
use crate::stm32::{SAI1, SAI2};
115+
use crate::pac::{SAI1, SAI2};
119116
use crate::time::Hertz;
120117

121118
/// SAI A sub-block.
@@ -175,7 +172,7 @@ where
175172
}
176173

177174
/// A filler type for when the MCK pin is unnecessary
178-
pub struct NoMck;
175+
pub type NoMck = NoPin;
179176

180177
macro_rules! pins {
181178
($($CH:ty: MCK: [$($MCK:ty),*] FS: [$($FS:ty),*] SCK: [$($SCK:ty),*] SD: [$($SD:ty),*])+) => {
@@ -206,32 +203,32 @@ pins! {
206203
SAI1A:
207204
MCK: [
208205
NoMck,
209-
PE2<Alternate<AF6>>
206+
gpio::PE2<AF6>
210207
]
211208
FS: [
212-
PE4<Alternate<AF6>>
209+
gpio::PE4<AF6>
213210
]
214211
SCK: [
215-
PE5<Alternate<AF6>>
212+
gpio::PE5<AF6>
216213
]
217214
SD: [
218-
PD6<Alternate<AF6>>,
219-
PE6<Alternate<AF6>>
215+
gpio::PD6<AF6>,
216+
gpio::PE6<AF6>
220217
]
221218
SAI1B:
222219
MCK: [
223220
NoMck,
224-
PF7<Alternate<AF6>>
221+
gpio::PF7<AF6>
225222
]
226223
FS: [
227-
PF9<Alternate<AF6>>
224+
gpio::PF9<AF6>
228225
]
229226
SCK: [
230-
PF8<Alternate<AF6>>
227+
gpio::PF8<AF6>
231228
]
232229
SD: [
233-
PE3<Alternate<AF6>>,
234-
PF6<Alternate<AF6>>
230+
gpio::PE3<AF6>,
231+
gpio::PF6<AF6>
235232
]
236233
}
237234

@@ -336,15 +333,15 @@ impl Deref for SAIA<SAI> {
336333
type Target = sai::CH;
337334

338335
fn deref(&self) -> &Self::Target {
339-
unsafe { &(*SAI::ptr()).cha }
336+
unsafe { &(*SAI::ptr()).cha() }
340337
}
341338
}
342339

343340
impl Deref for SAIB<SAI> {
344341
type Target = sai::CH;
345342

346343
fn deref(&self) -> &Self::Target {
347-
unsafe { &(*SAI::ptr()).chb }
344+
unsafe { &(*SAI::ptr()).chb() }
348345
}
349346
}
350347

@@ -400,17 +397,17 @@ where
400397
}
401398

402399
fn set_clock_gen(&self, sample_freq: Hertz, clocks: Clocks) {
403-
let mclk = sample_freq.0 * 256;
400+
let mclk = sample_freq.raw() * 256;
404401
// TODO: Use saib_clock for SAIB.
405-
let sai_clock = clocks.saia_clk().expect("no SAI clock available").0;
402+
let sai_clock = clocks.saia_clk().expect("no SAI clock available").raw();
406403
if (sai_clock + (mclk >> 1)) / mclk == 1 {
407404
// TODO: Typo in stm32f4
408-
self.cr1.modify(|_, w| unsafe { w.mcjdiv().bits(0) });
405+
self.cr1.modify(|_, w| unsafe { w.mckdiv().bits(0) });
409406
} else {
410407
let best_divider = (sai_clock + mclk) / (mclk << 1);
411408
assert!(best_divider < 16);
412409
self.cr1
413-
.modify(|_, w| unsafe { w.mcjdiv().bits(best_divider as u8) });
410+
.modify(|_, w| unsafe { w.mckdiv().bits(best_divider as u8) });
414411
}
415412
}
416413

@@ -503,7 +500,7 @@ where
503500
}
504501

505502
fn start(&self) {
506-
self.clrfr.modify(|_, w| {
503+
self.clrfr.write(|w| {
507504
w.clfsdet().set_bit();
508505
w.cafsdet().set_bit();
509506
w.ccnrdy().set_bit();

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