stm32-fmc

Author: burrbull

.github/workflows/ci.yml

@@ -41,7 +41,7 @@ jobs:
         rust:
           - stable
         features:
-          - usb_fs,sdio-host,can,i2s,fsmc_lcd,rtic1
+          - usb_fs,sdio-host,can,i2s,fsmc_lcd,rtic1,stm32-fmc
         include:
           - rust: nightly
             mcu: stm32f479

Cargo.toml

@@ -56,6 +56,8 @@ embedded-hal-async = { version = "1.0", optional = true }
 rtic = { version = "2.0.1", features = ["thumbv7-backend"], optional = true }
 atomic-polyfill = { version = "1.0.3", optional = true }
 
+stm32-fmc = { version = "0.3.0", optional = true }
+
 enumflags2 = "0.7.8"
 embedded-storage = "0.3"
 vcell = "0.1.3"
@@ -753,3 +755,7 @@ required-features = ["otg-fs", "usb_fs"] # stm32f401
 [[example]]
 name = "ws2812-spi"
 required-features = []
+
+[[example]]
+name = "fmc-sdram"
+required-features = ["stm32f469", "stm32-fmc"]

examples/fmc-sdram.rs

@@ -0,0 +1,135 @@
+//! This example shows how to use the FMC controller on the STM32F7 to communicate with an
+//! off-chip SDRAM memory device. The `stm32-fmc` crate does the majority of the work, and
+//! after initialization the SDRAM is memory mapped to the STM32F7 address space.
+//!
+//! This example was tested on the STM32F746G Discovery Board. The board has an IS42S32400F-6BL
+//! SDRAM chip, with only 16 of the 32 data wires connected to the microcontroller. This device
+//! is not explictly supported in the `stm32-fmc` crate at time of writing, but the IS42S16400J
+//! has very similar parameters and is used as a placeholder for now. Because of this, only half
+//! of the available memory space is available (128 Mb = 16 MB, so 8 MB available).
+//!
+//! To use the example, launch a GDB server and then `cargo run`. After several seconds, the
+//! message "Success!" should be printed in the GDB server terminal (via semihosting).
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate panic_semihosting;
+
+use core::{mem, slice};
+use cortex_m_rt::entry;
+use cortex_m_semihosting::hprintln;
+use stm32_fmc::devices::is42s16400j_7;
+use stm32f4xx_hal::{
+    fmc::FmcExt,
+    gpio::{alt::fmc as alt, Speed},
+    pac,
+    prelude::*,
+};
+
+/// Configure pins for the FMC controller
+macro_rules! fmc_pins {
+    ($($alt:ident: $pin:expr,)*) => {
+        (
+            $(
+                alt::$alt::from($pin.into_alternate()
+                    .speed(Speed::VeryHigh)
+                    .internal_pull_up(true)
+                )
+            ),*
+        )
+    };
+}
+
+#[entry]
+fn main() -> ! {
+    let cp = cortex_m::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Get the delay provider.
+    let clocks = dp.RCC.constrain().cfgr.sysclk(216.MHz()).freeze();
+    let mut delay = cp.SYST.delay(&clocks);
+
+    // IO
+    let gpioc = dp.GPIOC.split();
+    let gpiod = dp.GPIOD.split();
+    let gpioe = dp.GPIOE.split();
+    let gpiof = dp.GPIOF.split();
+    let gpiog = dp.GPIOG.split();
+    let gpioh = dp.GPIOH.split();
+
+    // Initialise SDRAM
+    let fmc_io = fmc_pins! {
+        A0: gpiof.pf0,
+        A1: gpiof.pf1,
+        A2: gpiof.pf2,
+        A3: gpiof.pf3,
+        A4: gpiof.pf4,
+        A5: gpiof.pf5,
+        A6: gpiof.pf12,
+        A7: gpiof.pf13,
+        A8: gpiof.pf14,
+        A9: gpiof.pf15,
+        A10: gpiog.pg0,
+        A11: gpiog.pg1,
+        Ba0: gpiog.pg4,
+        Ba1: gpiog.pg5,
+        D0: gpiod.pd14,
+        D1: gpiod.pd15,
+        D2: gpiod.pd0,
+        D3: gpiod.pd1,
+        D4: gpioe.pe7,
+        D5: gpioe.pe8,
+        D6: gpioe.pe9,
+        D7: gpioe.pe10,
+        D8: gpioe.pe11,
+        D9: gpioe.pe12,
+        D10: gpioe.pe13,
+        D11: gpioe.pe14,
+        D12: gpioe.pe15,
+        D13: gpiod.pd8,
+        D14: gpiod.pd9,
+        D15: gpiod.pd10,
+        Nbl0: gpioe.pe0,
+        Nbl1: gpioe.pe1,
+        Sdcke0: gpioc.pc3,
+        Sdclk: gpiog.pg8,
+        Sdncas: gpiog.pg15,
+        Sdne0: gpioh.ph3,
+        Sdnras: gpiof.pf11,
+        Sdnwe: gpioh.ph5,
+    };
+
+    // New SDRAM
+    let mut sdram = dp.FMC.sdram(fmc_io, is42s16400j_7::Is42s16400j {}, &clocks);
+
+    // Initialise controller and SDRAM
+    let len_bytes = (16 * 1024 * 1024) / 2;
+    let len_words = len_bytes / mem::size_of::<u32>();
+    let ram = unsafe {
+        let ram_ptr: *mut u32 = sdram.init(&mut delay);
+        slice::from_raw_parts_mut(ram_ptr, len_words)
+    };
+
+    // Access all the words in SDRAM (takes several seconds)
+    for addr in 0..len_words {
+        let val: u32 = addr as u32;
+
+        // Write
+        ram[addr] = val;
+
+        // Read
+        let res: u32 = ram[addr];
+        if res != val {
+            panic!(
+                "Error: Expected {} while reading address {:X} but got {}.",
+                val, addr, res
+            );
+        }
+    }
+
+    hprintln!("Success!");
+
+    loop {}
+}

src/fmc.rs

@@ -0,0 +1,206 @@
+//! HAL for Flexible memory controller (FMC)
+//!
+//! See the stm32-fmc [usage guide](https://github.com/stm32-rs/stm32-fmc#usage)
+
+// From stm32_fmc
+
+use stm32_fmc::FmcPeripheral;
+use stm32_fmc::{AddressPinSet, PinsSdram, Sdram, SdramChip, SdramPinSet, SdramTargetBank};
+
+use crate::rcc::{BusClock, Clocks, Enable, Reset};
+use fugit::HertzU32 as Hertz;
+
+use crate::gpio::alt::fmc as alt;
+
+#[cfg(feature = "fmc")]
+use crate::pac::FMC as FMC_PER;
+#[cfg(feature = "fsmc")]
+use crate::pac::FSMC as FMC_PER;
+
+/// Storage type for Flexible Memory Controller and its clocks
+pub struct FMC {
+    pub fmc: FMC_PER,
+    hclk: Hertz,
+}
+
+/// Extension trait for FMC controller
+pub trait FmcExt: Sized {
+    fn fmc(self, clocks: &Clocks) -> FMC;
+
+    /// A new SDRAM memory via the Flexible Memory Controller
+    fn sdram<
+        BANK: SdramPinSet,
+        ADDR: AddressPinSet,
+        PINS: PinsSdram<BANK, ADDR>,
+        CHIP: SdramChip,
+    >(
+        self,
+        pins: PINS,
+        chip: CHIP,
+        clocks: &Clocks,
+    ) -> Sdram<FMC, CHIP> {
+        let fmc = self.fmc(clocks);
+        Sdram::new(fmc, pins, chip)
+    }
+
+    /// A new SDRAM memory via the Flexible Memory Controller
+    fn sdram_unchecked<CHIP: SdramChip, BANK: Into<SdramTargetBank>>(
+        self,
+        bank: BANK,
+        chip: CHIP,
+        clocks: &Clocks,
+    ) -> Sdram<FMC, CHIP> {
+        let fmc = self.fmc(clocks);
+        Sdram::new_unchecked(fmc, bank, chip)
+    }
+}
+
+impl FmcExt for FMC_PER {
+    /// New FMC instance
+    fn fmc(self, clocks: &Clocks) -> FMC {
+        FMC {
+            fmc: self,
+            hclk: FMC_PER::clock(clocks),
+        }
+    }
+}
+
+unsafe impl FmcPeripheral for FMC {
+    const REGISTERS: *const () = FMC_PER::ptr() as *const ();
+
+    fn enable(&mut self) {
+        // TODO : change it to something safe ...
+        unsafe {
+            // Enable FMC
+            FMC_PER::enable_unchecked();
+            // Reset FMC
+            FMC_PER::reset_unchecked();
+        }
+    }
+
+    fn source_clock_hz(&self) -> u32 {
+        // FMC block is clocked by HCLK
+        self.hclk.raw()
+    }
+}
+
+macro_rules! pins {
+    ($($F:ident: $P:ident;)+) => {
+        $(
+            impl stm32_fmc::$F for alt::$P {}
+        )+
+    }
+}
+
+pins! {
+    A0: A0;
+    A1: A1;
+    A2: A2;
+    A3: A3;
+    A4: A4;
+    A5: A5;
+    A6: A6;
+    A7: A7;
+    A8: A8;
+    A9: A9;
+    A10: A10;
+    A11: A11;
+    A12: A12;
+    A13: A13;
+    A14: A14;
+    A15: A15;
+    A16: A16;
+    A17: A17;
+    A18: A18;
+    A19: A19;
+    A20: A20;
+    A21: A21;
+    A22: A22;
+    A23: A23;
+    A24: A24;
+    CLK: Clk;
+    D0: D0;
+    D1: D1;
+    D2: D2;
+    D3: D3;
+    D4: D4;
+    D5: D5;
+    D6: D6;
+    D7: D7;
+    D8: D8;
+    D9: D9;
+    D10: D10;
+    D11: D11;
+    D12: D12;
+    D13: D13;
+    D14: D14;
+    D15: D15;
+    DA0: Da0;
+    DA1: Da1;
+    DA2: Da2;
+    DA3: Da3;
+    DA4: Da4;
+    DA5: Da5;
+    DA6: Da6;
+    DA7: Da7;
+    DA8: Da8;
+    DA9: Da9;
+    DA10: Da10;
+    DA11: Da11;
+    DA12: Da12;
+    DA13: Da13;
+    DA14: Da14;
+    DA15: Da15;
+    NBL0: Nbl0;
+    NBL1: Nbl1;
+    // NCE: Nce;
+    NE1: Ne1;
+    NE2: Ne2;
+    NE3: Ne3;
+    NE4: Ne4;
+    NL: Nl;
+    NOE: Noe;
+    NWAIT: Nwait;
+    NWE: Nwe;
+}
+
+#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))]
+pins! {
+    BA0: Ba0;
+    BA1: Ba1;
+    SDCKE0: Sdcke0;
+    SDCKE1: Sdcke1;
+    SDCLK: Sdclk;
+    SDNCAS: Sdncas;
+    SDNE0: Sdne0;
+    SDNE1: Sdne1;
+    SDNRAS: Sdnras;
+    SDNWE: Sdnwe;
+}
+
+#[cfg(any(feature = "gpio-f427", feature = "gpio-f469"))]
+pins! {
+    D16: D16;
+    D17: D17;
+    D18: D18;
+    D19: D19;
+    D20: D20;
+    D21: D21;
+    D22: D22;
+    D23: D23;
+    D24: D24;
+    D25: D25;
+    D26: D26;
+    D27: D27;
+    D28: D28;
+    D29: D29;
+    D30: D30;
+    D31: D31;
+    NBL2: Nbl2;
+    NBL3: Nbl3;
+}
+
+#[cfg(feature = "gpio-f469")]
+pins! {
+    INT: Int;
+}

src/fsmc_lcd/pins.rs

@@ -17,7 +17,7 @@
 
 use core::marker::PhantomData;
 
-use crate::gpio::alt::fsmc as alt;
+use crate::gpio::alt::fmc as alt;
 
 use super::sealed;
 use super::{Lcd, SubBank1, Word};

src/gpio/alt/f4.rs

@@ -633,9 +633,12 @@ pub mod eth {
     }
 }
 
+#[cfg(any(feature = "fmc", feature = "fsmc"))]
+pub use fmc as fsmc;
+
 /// Pins available on all STM32F4 models that have an FSMC/FMC
 #[cfg(any(feature = "fmc", feature = "fsmc"))]
-pub mod fsmc {
+pub mod fmc {
     use super::*;
 
     pub use Ne1 as ChipSelect1;