Merge pull request #1159 from nicholasbishop/bishop-fix-riscv

phip1611 · web-flow · commit 110a4880be52 · 2024-05-06T06:08:56.000Z
Fix risc target_arch cfg
diff --git a/uefi/src/proto/debug/exception.rs b/uefi/src/proto/debug/exception.rs
@@ -140,7 +140,7 @@ impl ExceptionType {
     pub const MAX_AARCH64_EXCEPTION: ExceptionType = ExceptionType::EXCEPT_AARCH64_SERROR;
 }
 
-#[cfg(target_arch = "riscv")]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 impl ExceptionType {
     /// Instruction misaligned
     pub const EXCEPT_RISCV_INST_MISALIGNED: ExceptionType = ExceptionType(0);

Original file line number	Diff line number	Diff line change
`@@ -140,7 +140,7 @@ impl ExceptionType {`
`140`	`140`	`pub const MAX_AARCH64_EXCEPTION: ExceptionType = ExceptionType::EXCEPT_AARCH64_SERROR;`
`141`	`141`	`}`
`142`	`142`
`143`		`-#[cfg(target_arch = "riscv")]`
	`143`	`+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]`
`144`	`144`	`impl ExceptionType {`
`145`	`145`	`/// Instruction misaligned`
`146`	`146`	`pub const EXCEPT_RISCV_INST_MISALIGNED: ExceptionType = ExceptionType(0);`